82801FB Datasheet, PDF (243/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Register and Memory Mapping
6.4
Memory Map
Table 6-4 shows (from the processor perspective) the memory ranges that the ICH6 decodes.
Cycles that arrive from DMI that are not directed to any of the internal memory targets that decode
directly from DMI will be driven out on PCI unless the Substractive Decode Policy bit is set
(D31:F0:Offset 42h, bit 0). The ICH6 may then claim the cycle for the internal LAN controller.
PCI cycles generated by external PCI masters will be positively decoded unless they fall in the
PCI-to-PCI bridge memory forwarding ranges (those addresses are reserved for PCI peer-to-peer
traffic). If the cycle is not in the internal LAN controller’s range, it will be forwarded up to DMI.
Software must not attempt locks to the ICH6’s memory-mapped I/O ranges for EHCI and HPET. If
attempted, the lock is not honored which means potential deadlock conditions may occur.
Table 6-4. Memory Decode Ranges from Processor Perspective (Sheet 1 of 2)
Memory Range
0000 0000h–000D FFFFh
0010 0000h–TOM
(Top of Memory)
000E 0000h–000E FFFFh
000F 0000h–000F FFFFh
FEC0 0000h–FEC0 0100h
FFC0 0000h–FFC7 FFFFh
FF80 0000h–FF87 FFFFh
FFC8 0000h–FFCF FFFFh
FF88 0000h–FF8F FFFFh
FFD0 0000h–FFD7 FFFFh
FF90 0000h–FF97 FFFFh
FFD8 0000h–FFDF FFFFh
FF98 0000h–FF9F FFFFh
FFE0 000h–FFE7 FFFFh
FFA0 0000h–FFA7 FFFFh
FFE8 0000h–FFEF FFFFh
FFA8 0000h–FFAF FFFFh
FFF0 0000h–FFF7 FFFFh
FFB0 0000h–FFB7 FFFFh
FFF8 0000h–FFFF FFFFh
FFB8 0000h–FFBF FFFFh
FF70 0000h–FF7F FFFFh
FF30 0000h–FF3F FFFFh
FF60 0000h–FF6F FFFFh
FF20 0000h–FF2F FFFFh
FF50 0000h–FF5F FFFFh
FF10 0000h–FF1F FFFFh
FF40 0000h–FF4F FFFFh
FF00 0000h–FF0F FFFFh
Target
Dependency/Comments
Main Memory
TOM registers in Host controller
Firmware Hub
Bit 6 in Firmware Hub Decode Enable register is set
Firmware Hub
Bit 7 in Firmware Hub Decode Enable register is set
I/O APIC inside ICH6
Firmware Hub (or
PCI)³
Bit 8 in Firmware Hub Decode Enable register is set
Firmware Hub (or
PCI)³
Bit 9 in Firmware Hub Decode Enable register is set
Firmware Hub (or
PCI)³
Bit 10 in Firmware Hub Decode Enable register is set
Firmware Hub (or
PCI)³
Bit 11 in Firmware Hub Decode Enable register is set
Firmware Hub (or
PCI)³
Bit 12 in Firmware Hub Decode Enable register is set
Firmware Hub (or
PCI)³
Bit 13 in Firmware Hub Decode Enable register is set
Firmware Hub (or
PCI)³
Firmware Hub (or
PCI)³
Bit 14 in Firmware Hub Decode Enable register is set
Always enabled.
The top two, 64 KB blocks of this range can be
swapped, as described in Section 7.4.1.
Firmware Hub (or
PCI)³
Bit 3 in Firmware Hub Decode Enable register is set
Firmware Hub (or
PCI)³
Bit 2 in Firmware Hub Decode Enable register is set
Firmware Hub (or
PCI)³
Bit 1 in Firmware Hub Decode Enable register is set
Firmware Hub (or
PCI)³
Bit 0 in Firmware Hub Decode Enable register is set
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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