82801FB Datasheet, PDF (516/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

UHCI Controllers Registers
13.1.19 CWP—Core Well Policy Register
(USB—D29:F0/F1/F2/F3)
Address Offset: C8h
Default Value: 00h
Attribute: R/W
Size:
8 bits
Bit
Description
7:1 Reserved
Static Bus Master Status Policy Enable (SBMSPE) — R/W.
0 = The UHCI host controller dynamically sets the Bus Master status bit (Power Management 1
Status Register,[PMBASE+00h], bit 4) based on the memory accesses that are scheduled. The
default setting provides a more accurate indication of snoopable memory accesses in order to
0
help with software-invoked entry to C3 and C4 power states
1 = The UHCI host controller statically forces the Bus Master Status bit in power management
space to 1 whenever the HCHalted bit (USB Status Register, Base+02h, bit 5) is cleared.
NOTE: The PCI Power Management registers are enabled in the PCI Device 31: Function 0 space
(PM_IO_EN), and can be moved to any I/O location (128-byte aligned).
13.2 USB I/O Registers
Some of the read/write register bits that deal with changing the state of the USB hub ports function
such that on read back they reflect the current state of the port, and not necessarily the state of the
last write to the register. This allows the software to poll the state of the port and wait until it is in
the proper state before proceeding. A host controller reset, global reset, or port reset will
immediately terminate a transfer on the affected ports and disable the port. This affects the
USBCMD register, bit 4 and the PORTSC registers, bits [12,6,2]. See individual bit descriptions
for more detail.
Table 13-2. USB I/O Registers
BASE +
Offset
00–01h
02–03h
04–05h
06–07h
08–0Bh
0Ch
0D–0Fh
Mnemonic
Register Name
USBCMD
USBSTS
USBINTR
FRNUM
FRBASEADD
SOFMOD
—
USB Command
USB Status
USB Interrupt Enable
Frame Number
Frame List Base Address
Start of Frame Modify
Reserved
10–11h
PORTSC0 Port 0 Status/Control
12–13h
PORTSC1 Port 1 Status/Control
Default
0000h
0020h
0000h
0000h
Undefined
40h
—
0080h
0080h
Type
R/W
R/WC
R/W
R/W (see Note 1)
R/W
R/W
—
R/WC, RO, R/W
(see Note 1)
R/WC, RO, R/W
(see Note 1)
NOTES:
1. These registers are WORD writable only. Byte writes to these registers have unpredictable effects.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet