82801FB Datasheet, PDF (44/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Introduction
Table 1-1. Industry Specifications (Sheet 2 of 2)
Specification
Alert Standard Format Specification, Version 1.03
AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6)
IA-PC HPET (High Precision Event Timers) Specification,
Revision 0.98a
Location
http://www.dmtf.org/standards/asf
http://T13.org (T13 1410D)
http://www.intel.com/labs/platcomp/hpet/
hpetspec.htm
Chapter 1. Introduction
Chapter 1 introduces the ICH6 and provides information on manual organization and gives a
general overview of the ICH6.
Chapter 2. Signal Description
Chapter 2 provides a block diagram of the ICH6/ICH6-M and a detailed description of each signal.
Signals are arranged according to interface and details are provided as to the drive characteristics
(Input/Output, Open Drain, etc.) of all signals.
Chapter 3. ICH6 Pin States
Chapter 3 provides a complete list of signals, their associated power well, their logic level in each
suspend state, and their logic level before and after reset.
Chapter 4. System Clock Domains
Chapter 4 provides a list of each clock domain associated with the ICH6 in an ICH6 based system.
Chapter 5. Functional Description
Chapter 5 provides a detailed description of the functions in the ICH6. All PCI buses, devices and
functions in this document are abbreviated using the following nomenclature;
Bus:Device:Function. This document abbreviates buses as B0 and B1, devices as D8, D27, D28,
D29, D30 and D31 and functions as F0, F1, F2, F3, F4, F5, F6 and F7. For example Device 31
Function 0 is abbreviated as D31:F0, Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0.
Generally, the bus number will not be used, and can be considered to be Bus 0. Note that the
ICH6’s external PCI bus is typically Bus 1, but may be assigned a different number depending
upon system configuration.
Chapter 6. Register and Memory Mappings
Chapter 6 provides an overview of the registers, fixed I/O ranges, variable I/O ranges and memory
ranges decoded by the ICH6.
Chapter 7. Chipset Configuration Registers
Chapter 7 provides a detailed description of all registers and base functionality that is related to
chipset configuration and not a specific interface (such as LPC, PCI, or PCI Express). It contains
the root complex register block, which describes the behavior of the upstream internal link.
Chapter 8. LAN Controller Registers
Chapter 8 provides a detailed description of all registers that reside in the ICH6’s integrated LAN
controller. The integrated LAN controller resides on the ICH6’s external PCI bus (typically Bus 1)
at Device 8, Function 0 (B1:D8:F0).
Chapter 9. PCI-to-PCI Bridge Registers
Chapter 9 provides a detailed description of all registers that reside in the PCI-to-PCI bridge. This
bridge resides at Device 30, Function 0 (D30:F0).
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet