82801FB Datasheet, PDF (469/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.1.24 SDMA_TIM—Synchronous DMA Timing Register
(SATA–D31:F2)
Address Offset: 4A–4Bh
Default Value: 0000h
Attribute: R/W
Size:
16 bits
Note: This register is R/W to maintain software compatibility and enable parallel ATA functionality when
the PCI functions are combined. These bits have no effect on SATA operation, unless otherwise
noted.
Bit
Description
15:14
13:12
Reserved
Secondary Drive 1 Cycle Time (SCT1) — R/W. For Ultra ATA mode. The setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
SCB1 = 0 (33 MHz clk)
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks
10 = CT 2 clocks, RP 4 clocks
11 = Reserved
SCB1 = 1 (66 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 8 clocks
11 = Reserved
FAST_SCB1 = 1 (133 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 16 clocks
10 = Reserved
11 = Reserved
11:10
Reserved
Secondary Drive 0 Cycle Time (SCT0) — R/W. For Ultra ATA mode. The setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
SCB1 = 0 (33 MHz clk)
SCB1 = 1 (66 MHz clk) FAST_SCB1 = 1 (133 MHz clk)
9:8 _{00 = CT 4 clocks, RP 6 clocks}
00 = Reserved
00 = Reserved
01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks 01 = CT 3 clocks, RP 16 clocks
10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks
10 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
7:6 Reserved
Primary Drive 1 Cycle Time (PCT1) — R/W. For Ultra ATA mode, the setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
PCB1 = 0 (33 MHz clk)
PCB1 = 1 (66 MHz clk) FAST_PCB1 = 1 (133 MHz clk)
5:4 _{00 = CT 4 clocks, RP 6 clocks}
00 = Reserved
00 = Reserved
01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks 01 = CT 3 clocks, RP 16 clocks
10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks
10 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
3:2 Reserved
Primary Drive 0 Cycle Time (PCT0) — R/W. For Ultra ATA mode, the setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
PCB1 = 0 (33 MHz clk)
PCB1 = 1 (66 MHz clk) FAST_PCB1 = 1 (133 MHz clk)
1:0 _{00 = CT 4 clocks, RP 6 clocks}
00 = Reserved
00 = Reserved
01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks 01 = CT 3 clocks, RP 16 clocks
10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks
10 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
469