82801FB Datasheet, PDF (63/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Signal Description
2.10 Interrupt Interface
Table 2-10. Interrupt Signals
Name
Type
Description
SERIRQ
PIRQ[D:A]#
PIRQ[H:E]# /
GPI[5:2]
IDEIRQ
I/O
OD I
OD I
I
Serial Interrupt Request: This pin implements the serial interrupt protocol.
PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed to
interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering
section. Each PIRQx# line has a separate Route Control register.
In APIC mode, these signals are connected to the internal I/O APIC in the following
fashion: PIRQA# is connected to IRQ16, PIRQB# to IRQ17, PIRQC# to IRQ18, and
PIRQD# to IRQ19. This frees the legacy interrupts.
PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed to
interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering
section. Each PIRQx# line has a separate Route Control register.
In APIC mode, these signals are connected to the internal I/O APIC in the following
fashion: PIRQE# is connected to IRQ20, PIRQF# to IRQ21, PIRQG# to IRQ22, and
PIRQH# to IRQ23. This frees the legacy interrupts. If not needed for interrupts,
these signals can be used as GPI.
IDE Interrupt Request: This interrupt input is connected to the IDE drive.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
63