82801FB Datasheet, PDF (152/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
Table 5-25. State Transition Rules for Intel^® ICH6
Present
State
G0/S0/C0
Transition Trigger
• Processor halt instruction
• Level 2 Read
• Level 3 Read (Mobile Only)
• Level 4 Read (Mobile Only)
• SLP_EN bit set
• Power Button Override
• Mechanical Off/Power Failure
G0/S0/C1
G0/S0/C2
(Mobile
Only)
• Any Enabled Break Event
• STPCLK# goes active
• Power Button Override
• Power Failure
• Any Enabled Break Event
• Power Button Override
• Power Failure
• Previously in C3/C4 and bus masters
idle
G0/S0/C3
(Mobile
Only)
• Any Enabled Break Event
• Any Bus Master Event
• Power Button Override
• Power Failure
• Previously in C4 and bus masters idle
G0/S0/C4
(Mobile
Only)
G1/S1,
G1/S3, or
G1/S4
G2/S5
G3
• Any Enabled Break Event
• Any Bus Master Event
• Power Button Override
• Power Failure
• Any Enabled Wake Event
• Power Button Override
• Power Failure
• Any Enabled Wake Event
• Power Failure
• Power Returns
Next State
• G0/S0/C1
• G0/S0/C2
• G0/S0/C2, G0/S0/C3 or G0/S0/C4 -
depending on C4onC3_EN bit
(D31:F0:Offset A0h:bit 7) and
BM_STS_ZERO_EN bit (D31:F0:Offset A9h
:bit 2) (Mobile Only)
• G1/Sx or G2/S5 state
• G2/S5
• G3
• G0/S0/C0
• G0/S0/C2
• G2/S5
• G3
• G0/S0/C0
• G2/S5
• G3
• C3 or C4 - depending on PDME bit (D31:F0:
Offset A9h: bit 4)
• G0/S0/C0
• G0/S0/C2 - if PUME bit (D31:F0: Offset A9h:
bit 3) is set, else G0/S0/C0
• G2/S5
• G3
• C4 - depending on PDME bit (D31:F0: Offset
A9h: bit 4
• G0/S0/C0
• G0/S0/C2 - if PUME bit (D31:F0: Offset A9h:
bit 3) is set, else G0/S0/C0
• G2/S5
• G3
• G0/S0/C0 ¹
• G2/S5
• G3
• G0/S0/C0¹
• G3
• Optional to go to S0/C0 (reboot) or G2/S5
(stay off until power button pressed or other
wake event).^1,2
NOTES:
1. Transitions from the S1–S5 or G3 states to the S0 state are deferred until BATLOW# is inactive in mobile
configurations.
2. Some wake events can be preserved through power failure.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet