82801FB Datasheet, PDF (413/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
Bit
Description
SMBus Wake Status (SMB_WAK_STS) — R/WC. The SMBus controller can independently
cause an SMI# or SCI, so this bit does not need to do so (unlike the other bits in this register).
Software clears this bit by writing a 1 to it.
0 = Wake event Not caused by the ICH6’s SMBus logic.
1 = Set by hardware to indicate that the wake event was caused by the ICH6’s SMBus logic.This
bit will be set by the WAKE/SMI# command type, even if the system is already awake. The
SMI handler should then clear this bit.
NOTES:
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1. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the system is in the
S0 state. Therefore, to avoid an instant wake on subsequent transitions to sleep states,
software must clear this bit after each reception of the Wake/SMI# command or just prior to
entering the sleep state.
2. If SMB_WAK_STS is set due to SMBus slave receiving a message, it will be cleared by
internal logic when a THRMTRIP# event happens or a Power Button Override event.
However, THRMTRIP# or Power Button Override event will not clear SMB_WAK_STS if it is
set due to SMBALERT# signal going active.
3. The SMBALERT_STS bit (D31:F3:I/O Offset 00h:Bit 5) should be cleared by software before
the SMB_WAK_STS bit is cleared.
TCOSCI_STS — R/WC. Software clears this bit by writing a 1 to it.
6
0 = TOC logic did Not cause SCI.
1 = Set by hardware when the TCO logic causes an SCI.
AC97_STS — R/WC. This bit will be set to 1 when the codecs are attempting to wake the system
and the PME events for the codecs are armed for wakeup. A PME is armed by programming the
appropriate PMEE bit in the Power Management Control and Status register at bit 8 of offset 54h
in each AC ’97 function.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the codecs are attempting to wake the system. The AC97_STS bit
gets set only from the following two cases:
1.The PMEE bit for the function is set, and o The AC-link bit clock has been shut and the
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routed ACZ_SDIN line is high (for audio, if routing is disabled, no wake events are
allowed.
2.For modem, if audio routing is disabled, then the wake event is an OR of all ACZ_SDIN
lines. If routing is enabled, then the wake event for modem is the remaining non-routed
ACZ_SDIN line), or o GPI Status Change Interrupt bit (NABMBAR + 30h, bit 0) is 1.
NOTE: This bit is not affected by a hard reset caused by a CF9h write.
NOTE: This bit is also used for Intel High Definition Audio when ICH6 is configured to use the
Intel High Definition Audio host controller rather than the AC97 host controller.
USB2_STS — R/WC. Software clears this bit by writing a 1 to it.
4
0 = USB UHCI controller 2 does Not need to cause a wake.
1 = Set by hardware when USB UHCI controller 2 needs to cause a wake. Wake event will be
generated if the corresponding USB2_EN bit is set.
USB1_STS — R/WC. Software clears this bit by writing a 1 to it.
3
0 = USB UHCI controller 1 does Not need to cause a wake.
1 = Set by hardware when USB UHCI controller 1 needs to cause a wake. Wake event will be
generated if the corresponding USB1_EN bit is set.
2
Reserved
HOT_PLUG_STS — R/WC.
1
0 = This bit is cleared by writing a 1 to this bit position.
1 = When a PCI Express* Hot-Plug event occurs. This will cause an SCI if the HOT_PLUG_EN
bit is set in the GEP0_EN register.
Thermal Interrupt Status (THRM_STS) — R/WC. Software clears this bit by writing a 1 to it.
0 = THRM# signal Not driven active as defined by the THRM_POL bit
0
1 = Set by hardware anytime the THRM# signal is driven active as defined by the THRM_POL
bit. Additionally, if the THRM_EN bit is set, then the setting of the THRM_STS bit will also
generate a power management event (SCI or SMI#).
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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