82801FB Datasheet, PDF (596/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

AC ’97 Audio Controller Registers (D30:F2)
Note: Internal reset as a result of D3_HOT to D0 transition will reset all the core well registers except the
registers shared with the AC ’97 Modem (GCR, GSR, CASR). All resume well registers will not be
reset by the D3_HOT to D0 transition.
Core well registers and bits not reset by the D3_HOT to D0 transition:
• offset 2Ch–2Fh – bits 6:0 Global Control (GLOB_CNT)
• offset 30h–33h – bits [29,15,11:10,0] Global Status (GLOB_STA)
• offset 34h – Codec Access Semaphore Register (CAS)
Resume well registers and bits will not be reset by the D3_HOT to D0 transition:
• offset 30h–33h – bits [17:16] Global Status (GLOB_STA)
16.2.1
x_BDBAR—Buffer Descriptor Base Address Register
(Audio—D30:F2)
I/O Address:
Default Value:
Lockable:
NABMBAR + 00h (PIBDBAR), Attribute:
NABMBAR + 10h (POBDBAR),
NABMBAR + 20h (MCBDBAR)
MBBAR + 40h (MC2BDBAR)
MBBAR + 50h (PI2BDBAR)
MBBAR + 60h (SPBAR)
00000000h
Size:
No
Power Well:
R/W
32 bits
Core
Software can read the register at offset 00h by performing a single 32-bit read from address offset
00h. Reads across DWord boundaries are not supported.
Bit
Description
Buffer Descriptor Base Address[31:3] — R/W. These bits represent address bits 31:3. The data
31:3 should be aligned on 8-byte boundaries. Each buffer descriptor is 8 bytes long and the list can
contain a maximum of 32 entries.
2:0 Hardwired to 0.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet