82801FB Datasheet, PDF (196/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.19.6.1
Transaction-Based Interrupts
These interrupts are not signaled until after the status for the last complete transaction in the frame
has been written back to host memory. This guarantees that software can safely process through
(Frame List Current Index -1) when it is servicing an interrupt.
CRC Error / Time-Out
A CRC/Time-Out error occurs when a packet transmitted from the ICH6 to a USB device or a
packet transmitted from a USB device to the ICH6 generates a CRC error. The ICH6 is informed of
this event by a time-out from the USB device or by the ICH6’s CRC checker generating an error on
reception of the packet. Additionally, a USB bus time-out occurs when USB devices do not
respond to a transaction phase within 19-bit times of an EOP. Either of these conditions causes the
C_ERR field of the TD to decrement.
When the C_ERR field decrements to 0, the following occurs:
• The Active bit in the TD is cleared
• The Stalled bit in the TD is set
• The CRC/Time-out bit in the TD is set.
• At the end of the frame, the USB Error Interrupt bit is set in the HC status register.
If the CRC/Time out interrupt is enabled in the Interrupt Enable register, a hardware interrupt will
be signaled to the system.
Interrupt on Completion
Transfer Descriptors contain a bit that can be set to cause an interrupt on their completion. The
completion of the transaction associated with that block causes the USB Interrupt bit in the HC
Status Register to be set at the end of the frame in which the transfer completed. When a TD is
encountered with the IOC bit set to 1, the IOC bit in the HC Status register is set to 1 at the end of
the frame if the active bit in the TD is set to 0 (even if it was set to 0 when initially read).
If the IOC Enable bit of Interrupt Enable register (bit 2 of I/O offset 04h) is set, a hardware
interrupt is signaled to the system. The USB Interrupt bit in the HC status register is set either when
the TD completes successfully or because of errors. If the completion is because of errors, the USB
Error bit in the HC status register is also set.
Short Packet Detect
A transfer set is a collection of data which requires more than one USB transaction to completely
move the data across the USB. An example might be a large print file which requires numerous
TDs in multiple frames to completely transfer the data. Reception of a data packet that is less than
the endpoint’s Max Packet size during Control, Bulk or Interrupt transfers signals the completion
of the transfer set, even if there are active TDs remaining for this transfer set. Setting the SPD bit in
a TD indicates to the HC to set the USB Interrupt bit in the HC status register at the end of the
frame in which this event occurs. This feature streamlines the processing of input on these transfer
types. If the Short Packet Interrupt Enable bit in the Interrupt Enable register is set, a hardware
interrupt is signaled to the system at the end of the frame where the event occurred.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet