82801FB Datasheet, PDF (6/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Contents
5.9.4.4 Specific Rotation Mode (Specific Priority)............................................ 135
5.9.4.5 Poll Mode ............................................................................................. 135
5.9.4.6 Cascade Mode..................................................................................... 136
5.9.4.7 Edge and Level Triggered Mode.......................................................... 136
5.9.4.8 End of Interrupt (EOI) Operations ........................................................ 136
5.9.4.9 Normal End of Interrupt........................................................................ 136
5.9.4.10 Automatic End of Interrupt Mode ......................................................... 136
5.9.5 Masking Interrupts ............................................................................................... 137
5.9.5.1 Masking on an Individual Interrupt Request......................................... 137
5.9.5.2 Special Mask Mode.............................................................................. 137
5.9.6 Steering PCI Interrupts ........................................................................................ 137
5.10 Advanced Programmable Interrupt Controller
(APIC) (D31:F0)................................................................................................................ 138
5.10.1 Interrupt Handling ................................................................................................ 138
5.10.2 Interrupt Mapping................................................................................................. 138
5.10.3 PCI / PCI Express* Message-Based Interrupts ................................................... 139
5.10.4 Front Side Bus Interrupt Delivery......................................................................... 139
5.10.4.1 Edge-Triggered Operation ................................................................... 140
5.10.4.2 Level-Triggered Operation ................................................................... 140
5.10.4.3 Registers Associated with Front Side Bus
Interrupt Delivery.................................................................................. 140
5.10.4.4 Interrupt Message Format.................................................................... 140
5.11 Serial Interrupt (D31:F0) ................................................................................................... 141
5.11.1 Start Frame.......................................................................................................... 142
5.11.2 Data Frames ........................................................................................................ 142
5.11.3 Stop Frame .......................................................................................................... 142
5.11.4 Specific Interrupts Not Supported via SERIRQ ................................................... 143
5.11.5 Data Frame Format ............................................................................................. 143
5.12 Real Time Clock (D31:F0) ................................................................................................ 144
5.12.1 Update Cycles ..................................................................................................... 144
5.12.2 Interrupts.............................................................................................................. 145
5.12.3 Lockable RAM Ranges ........................................................................................ 145
5.12.4 Century Rollover .................................................................................................. 145
5.12.5 Clearing Battery-Backed RTC RAM .................................................................... 145
5.13 Processor Interface (D31:F0) ........................................................................................... 147
5.13.1 Processor Interface Signals................................................................................. 147
5.13.1.1 A20M# (Mask A20) .............................................................................. 147
5.13.1.2 INIT# (Initialization) .............................................................................. 147
5.13.1.3 FERR#/IGNNE# (Numeric Coprocessor Error /
Ignore Numeric Error) .......................................................................... 148
5.13.1.4 NMI (Non-Maskable Interrupt) ............................................................. 149
5.13.1.5 Stop Clock Request and Processor Sleep
(STPCLK# and CPUSLP#) .................................................................. 149
5.13.1.6 Processor Power Good (CPUPWRGOOD) ......................................... 149
5.13.1.7 Deeper Sleep (DPSLP#) (Mobile Only) ............................................... 149
5.13.2 Dual-Processor Issues (Desktop Only)................................................................ 149
5.13.2.1 Signal Differences................................................................................ 149
5.13.2.2 Power Management............................................................................. 150
5.14 Power Management (D31:F0) .......................................................................................... 150
5.14.1 Features............................................................................................................... 150
5.14.2 Intel^® ICH6 and System Power States ................................................................ 151
5.14.3 System Power Planes.......................................................................................... 153
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet