82801FB Datasheet, PDF (682/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI Express* Configuration Registers
19.1.9 CLS—Cache Line Size Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 0Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0
Base Class Code (BCC) — R/W. This is read/write but contains no functionality, per the PCI*
Express Base Specification.
19.1.10 PLT—Primary Latency Timer Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 0Dh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:3 Latency Count. Reserved per the PCI Express* Base Specification.
2:0 Reserved
19.1.11 HEADTYP—Header Type Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 0Eh
Default Value: 81h
Attribute:
Size:
RO
8 bits
Bit
Description
Multi-Function Device — RO.
7
0 = Single-function device.
1 = Multi-function device.
6:0 Configuration Layout. Hardwired to 01h, which indicates a PCI-to-PCI bridge.
19.1.12
BNUM—Bus Number Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 18–1Ah
Default Value: 000000h
Attribute:
Size:
R/W
24 bits
Bit
Description
23:16
15:8
7:0
Subordinate Bus Number (SBBN) — R/W. Indicates the highest PCI bus number below the
bridge.
Secondary Bus Number (SCBN) — R/W. Indicates the bus number the port.
Primary Bus Number (PBN) — R/W. Indicates the bus number of the backbone.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet