82801FB Datasheet, PDF (182/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.16.2.2
Bus Master IDE Timings
The timing modes used for Bus Master IDE transfers are identical to those for PIO transfers. The
DMA Timing Enable Only bits in IDE Timing register can be used to program fast timing mode for
DMA transactions only. This is useful for IDE devices whose DMA transfer timings are faster than
its PIO transfer timings. The IDE device DMA request signal is sampled on the same PCI clock
that DIOR# or DIOW# is de-asserted. If inactive, the DMA Acknowledge signal is de-asserted on
the next PCI clock and no more transfers take place until DMA request is asserted again.
5.16.2.3
Interrupts
The ICH6 can generate interrupts based upon a signal coming from the PATA device, or due to the
completion of a PRD with the ‘I’ bit set. The interrupt is edge triggered and active high. The PATA
host controller generates IDEIRQ.
When the ICH6 IDE controller is operating independently from the SATA controller (D31:F2),
IDEIRQ will generate IRQ14. When operating in conjunction with the SATA controller (combined
mode), IDE interrupts will still generate IDEIRQ, but this may in turn generate either IRQ14 or
IRQ15, depending upon the value of the MAP.MV (D31:F2:90h:bits 1:0) register. When in
combined mode and the SATA controller is emulating the logical secondary channel (MAP.MV =
1h), the PATA channel will emulate the logical primary channel and IDEIRQ will generate IRQ14.
Conversely, if the SATA controller in combined mode is emulating the logical primary channel
(MAP.MV=2h), IDEIRQ will generate IRQ15.
Note: IDE interrupts cannot be communicated through PCI devices or the serial IRQ stream.
5.16.2.4
Bus Master IDE Operation
To initiate a bus master transfer between memory and an IDE device, the following steps are
required:
1. Software prepares a PRD table in system memory. The PRD table must be DWord-aligned and
must not cross a 64-KB boundary.
2. Software provides the starting address of the PRD Table by loading the PRD Table Pointer
Register. The direction of the data transfer is specified by setting the Read/Write Control bit.
The interrupt bit and Error bit in the Status register are cleared.
3. Software issues the appropriate DMA transfer command to the disk device.
4. The bus master function is engaged by software writing a 1 to the Start bit in the Command
Register. The first entry in the PRD table is fetched and loaded into two registers which are not
visible by software, the Current Base and Current Count registers. These registers hold the
current value of the address and byte count loaded from the PRD table. The value in these
registers is only valid when there is an active command to an IDE device.
5. Once the PRD is loaded internally, the IDE device will receive a DMA acknowledge.
6. The controller transfers data to/from memory responding to DMA requests from the IDE
device. The IDE device and the host controller may or may not throttle the transfer several
times. When the last data transfer for a region has been completed on the IDE interface, the
next descriptor is fetched from the table. The descriptor contents are loaded into the Current
Base and Current Count registers.
7. At the end of the transfer, the IDE device signals an interrupt.
8. In response to the interrupt, software resets the Start/Stop bit in the command register. It then
reads the controller status followed by the drive status to determine if the transfer completed
successfully.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet