English
Language : 

82801FB Datasheet, PDF (708/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family
PCI Express* Configuration Registers
19.1.54
UEM — Uncorrectable Error Mask
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 148–14Bh
Default Value: 00000000h
Attribute:
Size:
R/WO, RO
32 bits
When set, the corresponding error in the UES register is masked, and the logged error will cause no
action. When cleared, the corresponding error is enabled.
Bit
Description
31:21
20
19
18
17
16
15
14
13
12
11:5
4
3:1
0
Reserved
Unsupported Request Error Mask (URE) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is masked.
ECRC Error Mask (EE) — RO. ECRC is not supported.
Malformed TLP Mask (MT) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is masked.
Receiver Overflow Mask (RO) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is masked.
Unexpected Completion Mask (UC) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is masked.
Completion Abort Mask (CA) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is masked.
Completion Timeout Mask (CT) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is masked.
Flow Control Protocol Error Mask (FCPE) — RO. Flow Control Protocol Errors not supported.
Poisoned TLP Mask (PT) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is masked.
Reserved
Data Link Protocol Error Mask (DLPE) — R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3:144) is masked.
Reserved
Training Error Mask (TE) — RO. Training Errors not supported
708
Intel® I/O Controller Hub 6 (ICH6) Family Datasheet