82801FB Datasheet, PDF (453/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

IDE Controller Registers (D31:F1)
11.2.2
11.2.3
BMISP—Bus Master IDE Status Register (IDE—D31:F1)
Address Offset: BMIBASE + 02h
Default Value: 00h
Attribute: R/WC
Size:
8 bits
Bit
Description
PRD Interrupt Status (PRDIS) — R/WC.
7 ^{0 = When this bit is cleared by software, the interrupt is cleared.}
1 = Set when the host controller completes execution of a PRD that has its Interrupt bit (bit 2 of this
register) set.
Drive 1 DMA Capable — R/W.
0 = Not Capable.
6 ^{1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 1 for this}
channel is capable of DMA transfers, and that the controller has been initialized for optimum
performance. The ICH6 does not use this bit. It is intended for systems that do not attach
BMIDE to the PCI bus.
Drive 0 DMA Capable — R/W.
0 = Not Capable
5 ^{1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 0 for this}
channel is capable of DMA transfers, and that the controller has been initialized for optimum
performance. The ICH6 does not use this bit. It is intended for systems that do not attach
BMIDE to the PCI bus.
4:3 Reserved. Returns 0.
Interrupt — R/WC. Software can use this bit to determine if an IDE device has asserted its interrupt
line (IDEIRQ).
0 = Software clears this bit by writing a 1 to it. If this bit is cleared while the interrupt is still active,
2
this bit will remain clear until another assertion edge is detected on the interrupt line.
1 = Set by the rising edge of the IDE interrupt line, regardless of whether or not the interrupt is
masked in the 8259 or the internal I/O APIC. When this bit is read as 1, all data transferred from
the drive is visible in system memory.
Error — R/WC.
1 ^{0 = Software clears this bit by writing a 1 to it.}
1 = This bit is set when the controller encounters a target abort or master abort when transferring
data on PCI.
Bus Master IDE Active (ACT) — RO.
0 = This bit is cleared by the ICH6 when the last transfer for a region is performed, where EOT for
that region is set in the region descriptor. It is also cleared by the ICH6 when the Start bit is
0
cleared in the Command register. When this bit is read as 0, all data transferred from the drive
during the previous bus master command is visible in system memory, unless the bus master
command was aborted.
1 = Set by the ICH6 when the Start bit is written to the Command register.
BMIDP—Bus Master IDE Descriptor Table Pointer Register
(IDE—D31:F1)
Address Offset: BMIBASE + 04h
Default Value: All bits undefined
Attribute: R/W
Size:
32 bits
Bit
Description
31:2
Address of Descriptor Table (ADDR) — R/W. This field corresponds to A[31:2]. The Descriptor
Table must be DWord-aligned. The Descriptor Table must not cross a 64-K boundary in memory.
1:0 Reserved
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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