82801FB Datasheet, PDF (180/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
If IORDY is asserted when the initial sample point is reached, no wait-states are added to the
command strobe assertion length. If IORDY is negated when the initial sample point is reached,
additional wait-states are added. Since the rising edge of IORDY must be synchronized, at least
two additional PCI clocks are added.
Shutdown latency is incurred after outstanding scheduled IDE data port transactions (either a
non-empty write post buffer or an outstanding read prefetch cycles) have completed and before
other transactions can proceed. It provides hold time on the DA[2:0] and CSxx# lines with respect
to the read and write strobes (DIOR# and DIOW#). Shutdown latency is two PCI clocks in
duration.
The IDE timings for various transaction types are shown in Table 5-40.
Table 5-40. IDE Transaction Timings (PCI Clocks)
IDE Transaction Type
Non-Data Port Compatible
Data Port Compatible
Fast Timing Mode
Startup
Latency
4
3
2
IORDY Sample
Point (ISP)
11
6
2–5
Recovery Time
(RCT)
22
14
1–4
Shutdown
Latency
2
2
2
5.16.1.2
IORDY Masking
The IORDY signal can be ignored and assumed asserted at the first IORDY Sample Point (ISP) on
a drive by drive basis via the IDETIM Register.
5.16.1.3
PIO 32-Bit IDE Data Port Accesses
A 32-bit PCI transaction run to the IDE data address (01F0h primary) results in two back to back
16-bit transactions to the IDE data port. The 32-bit data port feature is enabled for all timings, not
just enhanced timing. For compatible timings, a shutdown and startup latency is incurred between
the two, 16-bit halves of the IDE transaction. This guarantees that the chip selects are de-asserted
for at least two PCI clocks between the two cycles.
5.16.1.4
PIO IDE Data Port Prefetching and Posting
The ICH6 can be programmed via the IDETIM registers to allow data to be posted to and
prefetched from the IDE data ports.
Data prefetching is initiated when a data port read occurs. The read prefetch eliminates latency to
the IDE data ports and allows them to be performed back to back for the highest possible PIO data
transfer rates. The first data port read of a sector is called the demand read. Subsequent data port
reads from the sector are called prefetch reads. The demand read and all prefetch reads must be of
the same size (16 or 32 bits); software must not mix 32-bit and 16-bit reads.
Data posting is performed for writes to the IDE data ports. The transaction is completed on the PCI
bus after the data is received by the ICH6. The ICH6 then runs the IDE cycle to transfer the data to
the drive. If the ICH6 write buffer is non-empty and an unrelated (non-data or opposite channel)
IDE transaction occurs, that transaction will be stalled until all current data in the write buffer is
transferred to the drive. Only 16-bit buffer writes are supported.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet