82801FB Datasheet, PDF (169/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
Table 5-35. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2)
Restore Data
Restore Data
I/O
Addr
# of
Rds
Access
Data
20h 12
1 PIC ICW2 of Master controller
2 PIC ICW3 of Master controller
3 PIC ICW4 of Master controller
4
PIC OCW1 of Master controller¹
5 PIC OCW2 of Master controller
6 PIC OCW3 of Master controller
7 PIC ICW2 of Slave controller
8 PIC ICW3 of Slave controller
9 PIC ICW4 of Slave controller
10 PIC OCW1 of Slave controller¹
11 PIC OCW2 of Slave controller
12 PIC OCW3 of Slave controller
I/O
Addr
# of
Rds
Access
Data
1
DMA Chan 4–7 Command²
2 DMA Chan 4–7 Request
D0h 6
3 DMA Chan 4 Mode: Bits(1:0) = 00
4 DMA Chan 5 Mode: Bits(1:0) = 01
5 DMA Chan 6 Mode: Bits(1:0) = 10
6 DMA Chan 7 Mode: Bits(1:0) = 11.
NOTES:
1. The OCW1 register must be read before entering ALT access mode.
2. Bits 5, 3, 1, and 0 return 0.
5.14.10.2 PIC Reserved Bits
Many bits within the PIC are reserved, and must have certain values written in order for the PIC to
operate properly. Therefore, there is no need to return these values in ALT access mode. When
reading PIC registers from 20h and A0h, the reserved bits shall return the values listed in
Table 5-36.
Table 5-36. PIC Reserved Bits Return Values
PIC Reserved Bits
ICW2(2:0)
ICW4(7:5)
ICW4(3:2)
ICW4(0)
OCW2(4:3)
OCW3(7)
OCW3(5)
OCW3(4:3)
Value Returned
000
000
00
0
00
0
Reflects bit 6
01
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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