82801FB Datasheet, PDF (494/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.3.2.4
PxFBU—Port [3:0] FIS Base Address Upper 32-Bits
Register (D31:F2)
Address Offset:
Default Value:
Port 0: ABAR + 10Ch
Port 1: ABAR + 18Ch
Port 2: ABAR + 20Ch
Port 3: ABAR + 28Ch
Undefined
Attribute:
Size:
R/W
32 bits
12.3.2.5
Bit
Description
Command List Base Address Upper (CLBU) — R/W. This field indicates the upper 32-bits for the
31:3 ^{received FIS base for this port.}
Note that these bits are not reset on a HBA reset.
2:0 Reserved
PxIS—Port [3:0] Interrupt Status Register (D31:F2)
Address Offset:
Default Value:
Port 0: ABAR + 110h
Attribute:
Port 1: ABAR + 190h (Desktop Only)
Port 2: ABAR + 210h
Port 3: ABAR + 290h (Desktop Only)
00000000h
Size:
R/WC, RO
32 bits
Bit
Description
31 Cold Port Detect Status (CPDS) — RO. Cold presence not supported.
30
Task File Error Status (TFES) — R/WC. This bit is set whenever the status register is updated by
the device and the error bit (PxTFD.bit 0) is set.
Host Bus Fatal Error Status (HBFS) — R/WC. This bit indicates that the Intel^® ICH6 encountered
29 an error that it cannot recover from due to a bad software pointer. In PCI, such an indication would
be a target or master abort.
28
Host Bus Data Error Status (HBDS) — R/WC. Indicates that the ICH6 encountered a data error
(uncorrectable ECC / parity) when reading from or writing to system memory.
27
Interface Fatal Error Status (IFS) — R/WC. Indicates that the ICH6 encountered an error on the
SATA interface which caused the transfer to stop.
26
Interface Non-fatal Error Status (INFS) — R/WC. Indicates that the ICH6 encountered an error on
the SATA interface but was able to continue operation.
25 Reserved
24
Overflow Status (OFS) — R/WC. Indicates that the ICH6 received more bytes from a device than
was specified in the PRD table for the command.
Incorrect Port Multiplier Status (IPMS) — R/WC. Indicates that the ICH6 received a FIS from a
23 device whose Port Multiplier field did not match what was expected.
NOTE: Port Multiplier not supported by ICH6.
PhyRdy Change Status (PRCS) — RO. When set to 1 indicates the internal PhyRdy signal
changed state. This bit reflects the state of PxSERR.DIAG.N. Unlike most of the other bits in the
register, this bit is RO and is only cleared when PxSERR.DIAG.N is cleared.
22 _{Note that the internal PhyRdy signal also transitions when the port interface enters partial or slumber}
power management states. Partial and slumber must be disabled when Surprise Removal
Notification is desired, otherwise the power management state transitions will appear as false
insertion and removal events.
21:8 Reserved
494
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet