82801FB Datasheet, PDF (753/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Electrical Characteristics
Table 22-18. AC ’97 / Intel^® High Definition Audio Timing
Sym
Parameter
Min Max
t140 ACSDIN[2:0] Setup to Falling Edge of BITCLK
10 –
t141 ACSDIN[2:0] Hold from Falling Edge of BITCLK
10 –
t142
ACSYNC, ACSDOUTvalid delay from rising edge of
BITCLK
–
15
t143
Time duration for which SD0 is valid before BITCLK
edge.
7
–
t144
Time duration for which SDO is valid after BITCLK
edge.
7
–
t145 Setup time for SDI at rising edge of BITCLK
15 –
t146 Hold time for SDI at the rising edge of BITCLK
0
–
Units
ns
ns
ns
ns
ns
ns
ns
Fig
22-30
22-30
Notes
22-30
22-29
22-29
22-29
22-29
Table 22-19. LPC Timing
Sym
Parameter
t150 LAD[3:0] Valid Delay from PCICLK Rising
t151 LAD[3:0] Output Enable Delay from PCICLK Rising
t152 LAD[3:0] Float Delay from PCICLK Rising
t153 LAD[3:0] Setup Time to PCICLK Rising
t154 LAD[3:0] Hold Time from PCICLK Rising
t155 LDRQ[1:0]# Setup Time to PCICLK Rising
t156 LDRQ[1:0]# Hold Time from PCICLK Rising
t157 LFRAME# Valid Delay from PCICLK Rising
Min Max
2
11
2
–
28
7
–
0
–
12
–
0
–
2
12
Units
ns
ns
ns
ns
ns
ns
ns
ns
Fig
22-2
22-6
22-4
22-3
22-3
22-3
22-3
22-2
Notes
Table 22-20. Miscellaneous Timings
Sym
Parameter
t160 SERIRQ Setup Time to PCICLK Rising
t161 SERIRQ Hold Time from PCICLK Rising
t162 RI#, EXTSMI#, GPI, USB Resume Pulse Width
t163 SPKR Valid Delay from OSC Rising
t164 SERR# Active to NMI Active
t165 IGNNE# Inactive from FERR# Inactive
1
Min Max Units
Fig Notes
7
–
ns
22-3
0
–
ns
22-3
2
– RTCCLK 22-5
– 200
ns
22-2
– 200
ns
– 230
ns
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
753