82801FB Datasheet, PDF (155/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
Table 5-27. Causes of SMI# and SCI (Sheet 2 of 2)
Cause^1-5
SCI SMI
Additional Enables
Where Reported
BIOS_RLS written to
Yes
GBL_RLS written to
No
Write to B2h register
No
Periodic timer expires
No
64 ms timer expires
No
Enhanced USB Legacy Support
Event
No
Enhanced USB Intel Specific
Event
No
UHCI USB Legacy logic
No
Serial IRQ SMI reported
No
Device monitors match address in
its range
No
SMBus Host Controller
No
SMBus Slave SMI message
No
SMBus SMBALERT# signal active No
SMBus Host Notify message
received
No
(Mobile Only) BATLOW# assertion Yes
Access microcontroller 62h/66h
No
SLP_EN bit written to 1
No
No GBL_EN=1
Yes BIOS_EN=1
Yes APMC_EN = 1
Yes PERIODIC_EN=1
Yes SWSMI_TMR_EN=1
GBL_STS
BIOS_STS
APM_STS
PERIODIC_STS
SWSMI_TMR_STS
Yes LEGACY_USB2_EN = 1 LEGACY_USB2_STS
Yes INTEL_USB2_EN = 1
INTEL_USB2_STS
Yes LEGACY_USB_EN=1
LEGACY_USB_STS
Yes none
SERIRQ_SMI_STS
Yes none
DEVMON_STS,
DEVACT_STS
Yes
SMB_SMI_EN
Host Controller Enabled
SMBus host status reg.
Yes none
SMBus_SMI_STS
Yes none
SMBus_SMI_STS
Yes
HOST_NOTIFY_INTREN
SMBus_SMI_STS
HOST_NOTIFY_STS
Yes BATLOW_EN=1.
BATLOW_STS
Yes MCSMI_EN
MCSMI_STS
Yes SMI_ON_SLP_EN=1
SMI_ON_SLP_EN_STS
NOTES:
1. SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI.
2. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).
3. GBL_SMI_EN must be 1 to enable SMI.
4. EOS must be written to 1 to re-enable SMI for the next 1.
5. ICH6 must have SMI# fully enabled when ICH6 is also enabled to trap cycles. If SMI# is not enabled in
conjunction with the trap enabling, then hardware behavior is undefined.
6. When a power button override first occurs, the system will transition immediately to S5. The SCI will only
occur after the next wake to S0 if the residual status bit (PRBTNOR_STS) is not cleared prior to setting
SCI_EN.
7. Only GPI[15:0] may generate an SMI# or SCI.
5.14.4.1
PCI Express* SCI
PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using messages.
When a PME message is received, ICH6 will set the PCI_EXP_STS bit. If the PCI_EXP_EN bit is
also set, the ICH6 can cause an SCI via the GPE1_STS register.
5.14.4.2
PCI Express* Hot-Plug
PCI Express has a Hot-Plug mechanism and is capable of generating a SCI via the GPE1 register. It
is also capable of generating an SMI. However, it is not capable of generating a wake event.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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