82801FB Datasheet, PDF (402/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
Note: GPIOs that are not implemented will not have the corresponding bits implemented in this register.
10.8.2 APM I/O Decode
Table 10-10 shows the I/O registers associated with APM support. This register space is enabled in
the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved (fixed I/O location).
Table 10-10. APM Register Map
Address Mnemonic
Register Name
B2h
APM_CNT Advanced Power Management Control Port
B3h
APM_STS Advanced Power Management Status Port
Default
00h
00h
Type
R/W
R/W
10.8.2.1
APM_CNT—Advanced Power Management Control Port
Register
I/O Address:
Default Value:
Lockable:
Power Well:
B2h
00h
No
Core
Attribute:
Size:
Usage:
R/W
8-bit
Legacy Only
10.8.2.2
Bit
Description
This field is used to pass an APM command between the OS and the SMI handler. Writes to this
7:0 port not only store data in the APMC register, but also generates an SMI# when the APMC_EN bit is
set.
APM_STS—Advanced Power Management Status Port
Register
I/O Address:
Default Value:
Lockable:
Power Well:
B3h
00h
No
Core
Attribute:
Size:
Usage:
R/W
8-bit
Legacy Only
Bit
Description
7:0
This field is used to pass data between the OS and the SMI handler. Basically, this is a scratchpad
register and is not affected by any other register or function (other than a PCI reset).
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet