82801FB Datasheet, PDF (694/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI Express* Configuration Registers
19.1.29
LSTS—Link Status Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 52–53h
Default Value: See bit description
Attribute:
Size:
RO
16 bits
Bit
15:13
12
11
10
Description
Reserved
Slot Clock Configuration (SCC) — RO. Set to 1b to indicate that the Intel^® ICH6 uses the same
reference clock as on the platform and does not generate its own clock.
Link Training (LT) — RO. Default value is 0b.
0 = Link training completed.
1 = Link training is occurring.
Link Training Error (LTE) — RO. Not supported. Set value is 0b.
Negotiated Link Width (NLW) — RO. This field indicates the negotiated width of the given PCI
Express* link. The contents of this NLW field is undefined if the link has not successfully trained.
Port #
Possible Values
9:4
1
000001b, 000010b, 000100b
2
000001b
3
000001b
4
000001b
NOTE: 000001b = x1 link width, 0001000 = x4 link width (Enterprise applications only)
Link Speed (LS) — RO. This field indicates the negotiated Link speed of the given PCI Express*
3:0
link.
01h = Link is 2.5 Gb/s.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet