82801FB Datasheet, PDF (503/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.3.2.12 PxSERR—Port [3:0] Serial ATA Error Register (D31:F2)
Address Offset:
Default Value:
Port 0: ABAR + 130h
Attribute:
Port 1: ABAR + 1B0h (Desktop Only)
Port 2: ABAR + 230h
Port 3: ABAR + 2B0h (Desktop Only)
00000000h
Size:
R/WC
32 bits
Bit
Description
31:16
Diagnostics (DIAG) — R/WC. This field contains diagnostic error information for use by diagnostic
software in validating correct operation or isolating failure modes:
Bits Description
31:27 Reserved
26
Exchanged (X): When set to one this bit indicates a COMINIT signal was received. This bit
is reflected in the interrupt register PxIS.PCS.
25
Unrecognized FIS Type (F): Indicates that one or more FISs were received by the
Transport layer with good CRC, but had a type field that was not recognized.
24
Transport state transition error (T): Indicates that an error has occurred in the transition
from one state to another within the Transport layer since the last time this bit was cleared.
23
Link Sequence Error (S): Indicates that one or more Link state machine error conditions
was encountered. The Link Layer state machine defines the conditions under which the
link layer detects an erroneous transition.
22
Handshake Error (H): Indicates that one or more R_ERR handshake response was
received in response to frame transmission. Such errors may be the result of a CRC error
detected by the recipient, a disparity or 8b/10b decoding error, or other error condition
leading to a negative handshake on a transmitted frame.
21
CRC Error (C): Indicates that one or more CRC errors occurred with the Link Layer.
20
Disparity Error (D): This field is not used by AHCI.
19
10b to 8b Decode Error (B): Indicates that one or more 10b to 8b decoding errors
occurred.
18
Comm Wake (W): Indicates that a Comm Wake signal was detected by the Phy.
17
Phy Internal Error (I): Indicates that the Phy detected some internal error.
16
PhyRdy Change (N): When set to 1 this bit indicates that the internal PhyRdy signal
changed state since the last time this bit was cleared. In the ICH6, this bit will be set when
PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of this bit is then reflected in the
PxIS.PRCS interrupt status bit and an interrupt will be generated if enabled. Software
clears this bit by writing a 1 to it.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
503