82801FB Datasheet, PDF (530/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

EHCI Controller Registers (D29:F7)
14.1.4 PCISTS—PCI Status Register
(USB EHCI—D29:F7)
Address Offset: 06–07h
Default Value: 0290h
Attribute: R/W, RO
Size:
16 bits
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
effect.
Bit
Description
15 Detected Parity Error (DPE) — RO. Hardwired to 0.
Signaled System Error (SSE) — R/W.
14 ^{0 = No SERR# signaled by ICH6.}
1 = This bit is set by the ICH6 when it signals SERR# (internally). The SER_EN bit (bit 8 of the
Command Register) must be 1 for this bit to be set.
Received Master Abort (RMA) — R/W.
0 = No master abort received by EHC on a memory access.
13 _{1 = This bit is set when EHC, as a master, receives a master abort status on a memory access.}
This is treated as a Host Error and halts the DMA engines. This event can optionally generate
an SERR# by setting the SERR# Enable bit.
Received Target Abort (RTA) — R/W.
0 = No target abort received by EHC on memory access.
12 _{1 = This bit is set when EHC, as a master, receives a target abort status on a memory access. This}
is treated as a Host Error and halts the DMA engines. This event can optionally generate an
SERR# by setting the SERR# Enable bit (D29:F7:04h, bit 8).
Signaled Target Abort (STA) — RO. This bit is used to indicate when the EHCI function responds to
11 a cycle with a target abort. There is no reason for this to happen, so this bit will be
hardwired to 0.
10:9
DEVSEL# Timing Status (DEVT_STS) — RO. This 2-bit field defines the timing for DEVSEL#
assertion.
Master Data Parity Error Detected (DPED) — R/W.
0 = No data parity error detected on USB2.0 read completion packet.
8 _{1 = This bit is set by the ICH6 when a data parity error is detected on a USB 2.0 read completion}
packet on the internal interface to the EHCI host controller and bit 6 of the Command register is
set to 1.
7 Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
6 User Definable Features (UDF) — RO. Hardwired to 0.
5 66 MHz Capable (66 MHz _CAP) — RO. Hardwired to 0.
4
Capabilities List (CAP_LIST) — RO. Hardwired to 1 indicating that offset 34h contains a valid
capabilities pointer.
Interrupt Status — RO. This bit reflects the state of this function’s interrupt at the input of the
enable/disable logic.
3 0 = This bit will be 0 when the interrupt is de-asserted.
1 = This bit is a 1 when the interrupt is asserted.
The value reported in this bit is independent of the value in the Interrupt Enable bit.
2:0 Reserved
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet