82801FB Datasheet, PDF (552/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

EHCI Controller Registers (D29:F7)
14.2.2.3
USB2.0_INTR—USB 2.0 Interrupt Enable Register
Offset:
Default Value:
MEM_BASE + 28–2Bh
00000000h
Attribute: R/W
Size:
32 bits
This register enables and disables reporting of the corresponding interrupt to the software. When a
bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt
sources that are disabled in this register still appear in the USB2.0_STS Register to allow the
software to poll for events. Each interrupt enable bit description indicates whether it is dependent
on the interrupt threshold mechanism (see Section 4 of the EHCI specification), or not.
Bit
Description
31:6 Reserved. These bits are reserved and should be 0 when writing this register.
Interrupt on Async Advance Enable — R/W.
0 = Disable.
5 ^{1 = Enable. When this bit is a 1, and the Interrupt on Async Advance bit (D29:F7:CAPLENGTH +}
24h, bit 5) in the USB2.0_STS register is a 1, the host controller will issue an interrupt at the
next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on
Async Advance bit.
Host System Error Enable — R/W.
0 = Disable.
4 _{1 = Enable. When this bit is a 1, and the Host System Error Status bit (D29:F7:CAPLENGTH + 24h,}
bit 4) in the USB2.0_STS register is a 1, the host controller will issue an interrupt. The interrupt
is acknowledged by software clearing the Host System Error bit.
Frame List Rollover Enable — R/W.
0 = Disable.
3 _{1 = Enable. When this bit is a 1, and the Frame List Rollover bit (D29:F7:CAPLENGTH + 24h, bit 3)}
in the USB2.0_STS register is a 1, the host controller will issue an interrupt. The interrupt is
acknowledged by software clearing the Frame List Rollover bit.
Port Change Interrupt Enable — R/W.
0 = Disable.
2 _{1 = Enable. When this bit is a 1, and the Port Change Detect bit (D29:F7:CAPLENGTH + 24h, bit 2)}
in the USB2.0_STS register is a 1, the host controller will issue an interrupt. The interrupt is
acknowledged by software clearing the Port Change Detect bit.
USB Error Interrupt Enable — R/W.
0 = Disable.
1 ^{1 = Enable. When this bit is a 1, and the USBERRINT bit (D29:F7:CAPLENGTH + 24h, bit 1) in the}
USB2.0_STS register is a 1, the host controller will issue an interrupt at the next interrupt
threshold. The interrupt is acknowledged by software by clearing the USBERRINT bit in the
USB2.0_STS register.
USB Interrupt Enable — R/W.
0 = Disable.
0 ^{1 = Enable. When this bit is a 1, and the USBINT bit (D29:F7:CAPLENGTH + 24h, bit 0) in the}
USB2.0_STS register is a 1, the host controller will issue an interrupt at the next interrupt
threshold. The interrupt is acknowledged by software by clearing the USBINT bit in the
USB2.0_STS register.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet