82801FB Datasheet, PDF (522/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

UHCI Controllers Registers
13.2.5
FRBASEADD—Frame List Base Address Register
I/O Offset:
Default Value:
Base + (08–0Bh)
Undefined
Attribute:
Size:
R/W
32 bits
This 32-bit register contains the beginning address of the Frame List in the system memory. HCD
loads this register prior to starting the schedule execution by the host controller. When written, only
the upper 20 bits are used. The lower 12 bits are written as 0’s (4-KB alignment). The contents of
this register are combined with the frame number counter to enable the host controller to step
through the Frame List in sequence. The two least significant bits are always 00. This requires
DWord-alignment for all list entries. This configuration supports 1024 Frame List entries.
Bit
Description
31:12 Base Address — R/W. These bits correspond to memory address signals [31:12], respectively.
11:0 Reserved
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet