82801FB Datasheet, PDF (318/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LAN Controller Registers (B1:D8:F0)
8.3.16 FOR_ACT—Forced Actions Register
(ASF Controller—B1:D8:F0)
Offset Address: F3h
Default Value: 02h
Attribute:
Size:
R/W
8 bits
This register contains many different forcible actions including APM functions, flushing internal
pending SOS operations, software SOS operations, software reset, and EEPROM reload. Writes to
this register must only set one bit per-write. Setting multiple bits in a single write can have
indeterminate results.
Note: For bits in this register, writing a 1 invokes the operation. The bits self-clear immediately.
Bit
Description
Software Reset (FRC_RST) — R/W. This bit is used to reset the ASF controller. It performs the
7 equivalent of a hardware reset and re-read the EEPROM. This bit self-clears immediately. Software
should wait for the EEC_LOAD bit to clear.
Force EEPROM Reload (FRC_EELD) — R/W. Force Reload of EEPROM without affect current
monitoring state of the ASF controller. This bit self-clears immediately.
6 NOTE: Software registers in EEPROM are not loaded by this action. Software should disable the
ASF controller before issuing this command and wait for STA_LOAD to clear before
enabling again.
Flush SOS (FRC_FLUSH) — R/W. This bit is used to flush any pending SOSes or history internal to
5
the ASF controller. This is necessary because the Status register only shows events that have
happened as opposed to SOS events sent. Also, the history bits in the ASF controller are not
software visible. Self-clears immediately.
4 Reserved
3
Force APM Power Cycle (FRC_ACYC) — R/W. This mode forces the ASF controller to initiate a
power cycle to the system. The bit self-clears immediately.
2
Force APM Hard Power Down (FRC_AHDN) — R/W. This mode forces the ASF controller to
initiate a hard power down of the system immediately. The bit self-clears immediately.
Clear ASF Polling History (FRC_CLRAPOL) — R/W. Writing a 1b to this bit position will clear the
1 Poll History associated with all ASF Polling. Writing a 0b has no effect. This bit self-clears
immediately.
0
Force APM Reset (FRC_ARST) — R/W. This mode forces the ASF controller to initiate a hard reset
of the system immediately. The bit self-clears immediately.
8.3.17
RMCP_SNUM—RMCP Sequence Number Register
(ASF Controller—B1:D8:F0)
Offset Address: F4h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register is a means for software to read the current sequence number that hardware is using in
RMCP packets. Software can also change the value. Software should only write to this register
while the GLOBAL ENABLE is off.
Bit
Description
RMCP Sequence Number (RSEQ_VAL) — R/W. This is the current sequence number of the
RMCP packet being sent or the sequence number of the next RMCP packet to be sent. This value
7:0 can be set by software. At reset, it defaults to 00h. If the sequence number is not FFh, the ASF
controller will automatically increment this number by one (or rollover to 00h if incrementing from
FEh) after a successful RMCP packet transmission.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet