82801FB Datasheet, PDF (36/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Contents
5-5 Start Field Bit Definitions .......................................................................................................... 117
5-6 Cycle Type Bit Definitions......................................................................................................... 118
5-7 Transfer Size Bit Definition ....................................................................................................... 118
5-8 SYNC Bit Definition .................................................................................................................. 119
5-9 DMA Transfer Size ................................................................................................................... 123
5-10 Address Shifting in 16-Bit I/O DMA Transfers .......................................................................... 123
5-11 Counter Operating Modes ........................................................................................................ 129
5-12 Interrupt Controller Core Connections...................................................................................... 131
5-13 Interrupt Status Registers ......................................................................................................... 132
5-14 Content of Interrupt Vector Byte ............................................................................................... 132
5-15 APIC Interrupt Mapping ............................................................................................................ 138
5-16 Interrupt Message Address Format .......................................................................................... 140
5-17 Interrupt Message Data Format................................................................................................ 141
5-18 Stop Frame Explanation ........................................................................................................... 142
5-19 Data Frame Format .................................................................................................................. 143
5-20 Configuration Bits Reset by RTCRST# Assertion .................................................................... 146
5-21 INIT# Going Active ................................................................................................................... 148
5-22 NMI Sources............................................................................................................................. 149
5-23 DP Signal Differences .............................................................................................................. 149
5-24 General Power States for Systems Using Intel^® ICH6 ............................................................. 151
5-25 State Transition Rules for Intel^® ICH6 ...................................................................................... 152
5-26 System Power Plane ................................................................................................................ 153
5-27 Causes of SMI# and SCI .......................................................................................................... 154
5-28 Break Events (Mobile Only) ...................................................................................................... 156
5-29 Sleep Types.............................................................................................................................. 160
5-30 Causes of Wake Events ........................................................................................................... 161
5-31 GPI Wake Events ..................................................................................................................... 161
5-32 Transitions Due to Power Failure ............................................................................................. 162
5-33 Transitions Due to Power Button .............................................................................................. 164
5-34 Transitions Due to RI# Signal................................................................................................... 165
5-35 Write Only Registers with Read Paths in ALT Access Mode ................................................... 168
5-36 PIC Reserved Bits Return Values ............................................................................................ 169
5-37 Register Write Accesses in ALT Access Mode ........................................................................ 170
5-38 Intel^® ICH6 Clock Inputs........................................................................................................... 172
5-39 Heartbeat Message Data.......................................................................................................... 178
5-40 IDE Transaction Timings (PCI Clocks) .................................................................................... 180
5-41 Interrupt/Active Bit Interaction Definition .................................................................................. 183
5-42 Legacy Replacement Routing .................................................................................................. 191
5-43 Bits Maintained in Low Power States ....................................................................................... 198
5-44 USB Legacy Keyboard State Transitions ................................................................................. 200
5-45 UHCI vs. EHCI.......................................................................................................................... 201
5-46 Debug Port Behavior ................................................................................................................ 210
5-47 I²C Block Read ......................................................................................................................... 217
5-48 Enable for SMBALERT# ........................................................................................................... 220
5-49 Enables for SMBus Slave Write and SMBus Host Events ....................................................... 220
5-50 Enables for the Host Notify Command ..................................................................................... 220
5-51 Slave Write Registers ............................................................................................................... 222
5-52 Command Types ...................................................................................................................... 222
5-53 Read Cycle Format................................................................................................................... 223
5-54 Data Values for Slave Read Registers ..................................................................................... 224
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet