82801FB Datasheet, PDF (617/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

AC ’97 Modem Controller Registers (D30:F3)
These registers exist in I/O space and reside in the AC ’97 controller. The two channels, Modem in
and Modem out, each have their own set of Bus Mastering registers. The following register
descriptions apply to both channels. The naming prefix convention used is as follows:
MI = Modem in channel
MO = Modem out channel
Table 17-3. Modem Registers
Offset
00h–03h
04h
05h
06h–07h
08h–09h
0Ah
Mnemonic
MI_BDBAR
MI_CIV
MI_LVI
MI_SR
MI_PICB
MI_PIV
Name
Modem In Buffer Descriptor List Base
Address
Modem In Current Index Value
Modem In Last Valid Index
Modem In Status
Modem In Position In Current Buffer
Modem In Prefetch Index Value
0Bh
MI_CR
Modem In Control
10h–13h
14h
15h
16h–17h
18h–19h
1Ah
MO_BDBAR
MO_CIV
MO_LVI
MO_SR
MI_PICB
MO_PIV
Modem Out Buffer Descriptor List Base
Address
Modem Out Current Index Value
Modem Out Last Valid
Modem Out Status
Modem In Position In Current Buffer
Modem Out Prefetched Index
1Bh
MO_CR Modem Out Control
3Ch–3Fh GLOB_CNT Global Control
40h–43h
44h
GLOB_STA Global Status
CAS
Codec Access Semaphore
Default
00000000h
00h
00h
0001h
0000h
00h
00h
00000000h
00h
00h
0001h
0000h
00h
00h
00000000h
00300000h
00h
Access
R/W
RO
R/W
R/WC, RO
RO
RO
R/W,
R/W (special)
R/W
RO
R/W
R/WC, RO
RO
RO
R/W,
R/W (special)
R/W,
R/W (special)
RO, R/W,
R/WC
R/W (special)
NOTE:
1. MI = Modem in channel; MO = Modem out channel
Note:
Internal reset as a result of D3_HOT to D0 transition will reset all the core well registers except the
registers shared with the AC ’97 audio controller (GCR, GSR, CASR). All resume well registers
will not be reset by the D3_HOT to D0 transition.
Core well registers and bits not reset by the D3_HOT to D0 transition:
• offset 3Ch–3Fh – bits [6:0] Global Control (GLOB_CNT)
• offset 40h–43h – bits [29,15,11:10] Global Status (GLOB_STA)
• offset 44h – Codec Access Semaphore Register (CAS)
Resume well registers and bits will not be reset by the D3_HOT to D0 transition:
• offset 40h–43h – bits [17:16] Global Status (GLOB_STA)
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
617