82801FB Datasheet, PDF (343/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10 LPC Interface Bridge Registers
(D31:F0)
The LPC bridge function of the ICH6 resides in PCI Device 31:Function 0. This function contains
many other functional units, such as DMA and Interrupt controllers, Timers, Power Management,
System Management, GPIO, RTC, and LPC Configuration Registers.
Registers and functions associated with other functional units (EHCI, UHCI, IDE, etc.) are
described in their respective sections.
10.1 PCI Configuration Registers (LPC I/F—D31:F0)
Note: Address locations that are not shown should be treated as Reserved.
.
Table 10-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 1 of 2)
Offset
00–01h
02–03h
04–05h
06–07h
08h
09h
0Ah
0Bh
0Dh
0Eh
2C–2Fh
40–43h
44h
48–4Bh
4C
60–63h
64h
68–6Bh
80h
82–83h
Mnemonic
VID
Register Name
Vendor Identification
DID
Device Identification
PCICMD
PCISTS
RID
PCI Command
PCI Status
Revision Identification
PI
SCC
BCC
PLT
HEADTYP
SS
PMBASE
ACPI_CNTL
GPIOBASE
GC
PIRQ[n]_ROUT
SIRQ_CNTL
PIRQ[n]_ROUT
LPC_I/O_DEC
LPC_EN
Programming Interface
Sub Class Code
Base Class Code
Primary Latency Timer
Header Type
Sub System Identifiers
ACPI Base Address
ACPI Control
GPIO Base Address
GPIO Control
PIRQ[A–D] Routing Control
Serial IRQ Control
PIRQ[E–H] Routing Control
I/O Decode Ranges
LPC I/F Enables
Default
8086h
2641h ICH6-M
2640h ICH6/ICH6R
0007h
0200h
See register
description.
00h
01h
06h
00h
80h
00000000h
00000001h
00h
00000001h
00h
80h
10h
80h
0000h
0000h
Type
RO
RO
R/W, RO
R/WC, RO
RO
RO
RO
RO
RO
RO
R/WO
R/W, RO
R/W
R/W, RO
R/W
R/W
R/W, RO
R/W
R/W
R/W
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
343