82801FB Datasheet, PDF (435/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.10.7
GPIO_USE_SEL2—GPIO Use Select 2 Register[63:32]
Offset Address:
Default Value:
Lockable:
GPIOBASE +30h
00000006h
No
Attribute:
Size:
Power Well:
R/W
32-bit
Processor I/O for 17, Core
for 16:0
Bit
Description
GPIO_USE_SEL2[49, 41:40] — R/W. Each bit in this register enables the corresponding GPIO (if it
exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
After a full reset (RSMRST#) all multiplexed signals in the resume and core wells are configured as
a GPIO rather than as their native function. After just a PLTRST#, the GPIO in the core well are
configured as GPIO.
17, 9:8
NOTES:
1. The following bits are not implemented because there is no corresponding GPIO: 3:7, 10:15,
18:31.
2. The following bits are always 1 because they are unmultiplexed: 1:2
3. Bit 16 is not implemented because the GPIO selection will be controlled by Bit 8 (REQ/GNT pair)
4. If GPIO[n] does not exist, then the bit in this register will always read as 0 and writes will have no
effect.
5. The following bits are not implemented because they are determined by the Desktop/Mobile
configuration: 0
10.10.8
GP_IO_SEL2—GPIO Input/Output Select 2 Register[63:32]
Offset Address:
Default Value:
Lockable:
GPIOBASE +34h
00000300h
No
Attribute:
Size:
Power Well:
R/W
32-bit
Core
Bit
Description
31:18 Always 0. No corresponding GPIO.
17:16 Always 0. Outputs.
15:10 Always 0. No corresponding GPIO.
9:8 Always 0. Inputs.
7:3 Always 0. No corresponding GPIO.
GP_IO_SEL2[34:32] — R/W.
2:0 ^{0 = GPIO signal is programmed as an output.}
1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL2 register) is programmed as an
input.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
435