82801FB Datasheet, PDF (157/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
Table 5-28. Break Events (Mobile Only) (Sheet 2 of 2)
Event
Breaks from
Comment
Any internal event that cause
INIT# to go active
Any bus master request (internal,
external or DMA, or BMBUSY#)
goes active and BM_RLD=1
(D31:F0:Offset PMBASE+04h: bit
1)
Processor Pending Break Event
Indication
C2, C3, C4
C3, C4
C2, C3, C4
Could be indicated by the keyboard controller via the
RCIN input signal.
Need to wake up processor so it can do snoops
Note: If the PUME bit (D31:F0: Offset A9h: bit 3) is set,
then bus master activity will NOT be treated as a break
event. Instead, there will be a return only to the C2 state.
Only available if FERR# enabled for break event
indication (See FERR# Mux Enable in GCS, Chipset
Configuration Registers:Offset 3410h:bit 6)
5.14.5.1
Transition Rules among S0/Cx and Throttling States
The following priority rules and assumptions apply among the various S0/Cx and throttling states:
• Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This is because
the processor can only perform one register access at a time and Sleep states have higher
priority than thermal throttling.
• When the SLP_EN bit is set (system going to a S1 - S5 sleep state), the THTL_EN and
FORCE_THTL bits can be internally treated as being disabled (no throttling while going to
sleep state).
• (Mobile Only) If the THTL_EN or FORCE_THTL bits are set, and a Level 2, Level 3 or Level
4 read then occurs, the system should immediately go and stay in a C2, C3 or C4 state until a
break event occurs. A Level 2, Level 3 or Level 4 read has higher priority than the software
initiated throttling.
• (Mobile Only) After an exit from a C2, C3 or C4 state (due to a Break event), and if the
THTL_EN or FORCE_THTL bits are still set the system will continue to throttle STPCLK#.
Depending on the time of break event, the first transition on STPCLK# active can be delayed
by up to one THRM period (1024 PCI clocks = 30.72 µs).
• The Host controller must post Stop-Grant cycles in such a way that the processor gets an
indication of the end of the special cycle prior to the ICH6 observing the Stop-Grant cycle.
This ensures that the STPCLK# signals stays active for a sufficient period after the processor
observes the response phase.
• (Mobile Only) If in the C1 state and the STPCLK# signal goes active, the processor will
generate a Stop-Grant cycle, and the system should go to the C2 state. When STPCLK# goes
inactive, it should return to the C1 state.
5.14.5.2
Deferred C3/C4 (Mobile Only)
Due to the new DMI protocol, if there is any bus master activity (other than true isoch), then the C0
to C3 transition will pause at the C2 state. ICH6 will keep the processor in a C2 state until:
• ICH6 sees no bus master activity.
• A break event occurs. In this case, the ICH6 will perform the C2 to C0 sequence. Note that bus
master traffic is not a break event in this case.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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