82801FB Datasheet, PDF (149/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.13.1.4 NMI (Non-Maskable Interrupt)
Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in Table 5-22.
Table 5-22. NMI Sources
Cause of NMI
Comment
SERR# goes active (either internally, externally Can instead be routed to generate an SCI, through the
via SERR# signal, or via message from
NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h,
(G)MCH)
bit 11).
IOCHK# goes active via SERIRQ# stream
(ISA system Error)
Can instead be routed to generate an SCI, through the
NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h,
bit 11).
5.13.1.5
Stop Clock Request and Processor Sleep
(STPCLK# and CPUSLP#)
The ICH6 power management logic controls these active-low signals. Refer to Section 5.14 for
more information on the functionality of these signals.
5.13.1.6
Processor Power Good (CPUPWRGOOD)
This signal is connected to the processor’s PWRGOOD input. In mobile configurations to allow for
Intel SpeedStep technology support, this signal is kept high during an Intel SpeedStep technology
state transition to prevent loss of processor context. This is an open-drain output signal (external
pull-up resistor required) that represents a logical AND of the ICH6’s PWROK and VRMPWRGD
signals.
5.13.1.7
Deeper Sleep (DPSLP#) (Mobile Only)
This active-low signal controls the internal gating of the processor’s core clock. This signal asserts
before and de-asserts after the STP_CPU# signal to effectively stop the processor’s clock
(internally) in the states in which STP_CPU# can be used to stop the processor’s clock externally.
5.13.2 Dual-Processor Issues (Desktop Only)
5.13.2.1 Signal Differences
In dual-processor designs, some of the processor signals are unused or used differently than for
uniprocessor designs.
Table 5-23. DP Signal Differences
Signal
A20M# / A20GATE
STPCLK#
FERR# / IGNNE#
Difference
Generally not used, but still supported by Intel^® ICH6.
Used for S1 State as well as preparation for entry to S3–S5
Also allows for THERM# based throttling (not via ACPI control methods). Should be
connected to both processors.
Generally not used, but still supported by ICH6.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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