82801FB Datasheet, PDF (656/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Intel^® High Definition Audio Controller Registers (D27:F0)
18.2.7
18.2.8
18.2.9
WAKEEN—Wake Enable Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address: HDBAR + 0Ch
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
Description
15:3 Reserved.
SDIN Wake Enable Flags — R/W. These bits control which SDI signal(s) may generate a wake
event. A 1b in the bit mask indicates that the associated SDIN signal is enabled to generate a wake.
Bit 0 is used for SDI[0]
2:0 ^{Bit 1 is used for SDI[1]}
Bit 2 is used for SDI[2]
NOTE: These bits are in the resume well and only cleared on a power on reset. Software must not
make assumptions about the reset state of these bits and must set them appropriately.
STATESTS—State Change Status Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address: HDBAR + 0Eh
Default Value: 0000h
Attribute:
Size:
R/WC
16 bits
Bit
Description
15:3 Reserved.
SDIN State Change Status Flags — R/WC. Flag bits that indicate which SDI signal(s) received a
state change event. The bits are cleared by writing 1s to them.
Bit 0 = SDI[0]
2:0 ^{Bit 1 = SDI[1]}
Bit 2 = SDI[2]
NOTE: These bits are in the resume well and only cleared on a power on reset. Software must not
make assumptions about the reset state of these bits and must set them appropriately.
GSTS—Global Status Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address: HDBAR + 10h
Default Value: 0000h
Attribute:
Size:
R/WC
16 bits
Bit
Description
15:2 Reserved.
Flush Status — R/WC. This bit is set to 1 by hardware to indicate that the flush cycle initiated when
1 the Flush Control bit (HDBAR + 08h, bit 1) was set has completed. Software must write a 1 to clear
this bit before the next time the Flush Control bit is set to clear the bit.
0 Reserved.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet