82801FB Datasheet, PDF (222/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.21.7.1 Format of Slave Write Cycle
The external master performs Byte Write commands to the ICH6 SMBus slave interface. The
“Command” field (bits 11:18) indicate which register is being accessed. The Data field (bits 20:27)
indicate the value that should be written to that register. Table 5-51 has the values associated with
the registers.
Table 5-51. Slave Write Registers
Register
0
1–3
4
5
6–7
8
9–FFh
Function
Command Register. See Table 5-52 below for legal values written to this register.
Reserved
Data Message Byte 0
Data Message Byte 1
Reserved
Reserved
Reserved
NOTE: The external microcontroller is responsible to make sure that it does not update the contents of the data
byte registers until they have been read by the system processor. The ICH6 overwrites the old value
with any new value received. A race condition is possible where the new value is being written to the
register just at the time it is being read. ICH6 will not attempt to cover this race condition
(i.e., unpredictable results in this case).
.
Table 5-52. Command Types (Sheet 1 of 2)
Command
Type
Description
0
Reserved
WAKE/SMI#. This command wakes the system if it is not already awake. If system is already
awake, an SMI# is generated.
1
NOTE: The SMB_WAK_STS bit will be set by this command, even if the system is already
awake. The SMI handler should then clear this bit.
2
Unconditional Powerdown. This command sets the PWRBTNOR_STS bit, and has the same
effect as the Powerbutton Override occurring.
HARD RESET WITHOUT CYCLING: This command causes a hard reset of the system (does
3
not include cycling of the power supply). This is equivalent to a write to the CF9h register with
bits 2:1 set to 1, but bit 3 set to 0.
4
HARD RESET SYSTEM. This command causes a hard reset of the system (including cycling of
the power supply). This is equivalent to a write to the CF9h register with bits 3:1 set to 1.
Disable the TCO Messages. This command will disable the Intel^® ICH6 from sending
5
Heartbeat and Event messages (as described in Section 5.15.2). Once this command has been
executed, Heartbeat and Event message reporting can only be re-enabled by assertion and de-
assertion of the RSMRST# signal.
6
WD RELOAD: Reload watchdog timer.
7
Reserved
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet