82801FB Datasheet, PDF (567/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SMBus Controller Registers (D31:F3)
15.1.10
SVID—Subsystem Vendor Identification Register
(SMBus—D31:F2/F4)
Address Offset:
Default Value:
Lockable:
2Ch–2Dh
0000h
No
Attribute:RO
Size: 16 bits
Power Well:Core
Bit
Description
Subsystem Vendor ID (SVID) — RO. The SVID register, in combination with the Subsystem ID (SID)
register, enables the operating system (OS) to distinguish subsystems from each other. The value
15:0
returned by reads to this register is the same as that which was written by BIOS into the IDE SVID
register.
NOTE: Software can write to this register only once per core well reset. Writes should be done as a
single 16-bit cycle.
15.1.11
SID—Subsystem Identification Register
(SMBus—D31:F2/F4)
Address Offset:
Default Value:
Lockable:
2Eh–2Fh
0000h
No
Attribute:R/WO
Size: 16 bits
Power Well:Core
Bit
Description
Subsystem ID (SID) — RO. The SID register, in combination with the SVID register, enables the
operating system (OS) to distinguish subsystems from each other. The value returned by reads to
15:0 this register is the same as that which was written by BIOS into the IDE SID register.
NOTE: Software can write to this register only once per core well reset. Writes should be done as a
single 16-bit cycle.
15.1.12
INT_LN—Interrupt Line Register (SMBus—D31:F3)
Address Offset: 3Ch
Default Value: 00h
Attributes: R/W
Size:
8 bits
Bit
Description
7:0
Interrupt Line (INT_LN) — R/W. This data is not used by the ICH6. It is to communicate to software
the interrupt line that the interrupt pin is connected to PIRQB#.
15.1.13
INT_PN—Interrupt Pin Register (SMBus—D31:F3)
Address Offset: 3Dh
Default Value: See description
Attributes: RO
Size:
8 bits
Bit
Description
7:0
Interrupt PIN (INT_PN) — RO. This field reflects the value of D31IP.SMIP in chipset configuration
space.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
567