82801FB Datasheet, PDF (186/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.17 SATA Host Controller (D31:F2)
The SATA function in the ICH6 has dual modes of operation to support different operating system
conditions. In the case of Native IDE enabled operating systems, the ICH6 has separate PCI
functions for serial and parallel ATA (“enhanced mode”). To support legacy operating systems,
there is only one PCI function for both the serial and parallel ATA ports if functionality from both
SATA and PATA devices is desired (“combined mode”).
The MAP register, Section 12.1.29, provides the ability to share PCI functions. When sharing is
enabled, all decode of I/O is done through the SATA registers. Device 31, Function 1
(IDE controller) is hidden by software writing to the Function Disable Register (D31, F0,
offset F2h, bit 1), and its configuration registers are not used.
The ICH6 SATA controller features four (desktop only) / two (mobile only) sets of interface signals
(ports) that can be independently enabled or disabled (they cannot be tri-stated or driven low). Each
interface is supported by an independent DMA controller.
The ICH6 SATA controller interacts with an attached mass storage device through a register
interface that is equivalent to that presented by a traditional IDE host adapter. The host software
follows existing standards and conventions when accessing the register interface and follows
standard command protocol conventions.
Note: SATA interface transfer rates are independent of UDMA mode settings. SATA interface transfer
rates will operate at the bus’s maximum speed, regardless of the UDMA mode reported by the
SATA device or the system BIOS.
5.17.1 Theory of Operation
5.17.1.1
Standard ATA Emulation
The ICH6 contains a set of registers that shadow the contents of the legacy IDE registers. The
behavior of the Command and Control Block registers, PIO, and DMA data transfers, resets, and
interrupts are all emulated.
Note: The ICH6 requires that software wait for BSY=0 and DRDY=1 after drive power-up before
writing to the Device Control Register. Further, it is recommended that software perform the
following steps for each SATA channel before unmasking the SATA controller’s IRQ:
1. Read the (Task File) Status Register of each attached device.
2. Read the existing Bus Master Status register value.
3. OR that value with 4
4. Write the resulting value back to the Bus Master Status register.
The ICH6 will assert INTR when the master device completes the EDD (Execute Device
Diagnostics) command regardless of the command completion status of the slave device. If the
master completes EDD first, an INTR is generated and BSY will remain ‘1’ until the slave
completes the command. If the slave completes EDD first, BSY will be ‘0’ when teh master
completes the EDD command and asserts INTR. Software must wait for BSY to clear before
completing an EDD command, as required by the ATA5 through ATA7 (T13) industry
specifications.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet