82801FB Datasheet, PDF (8/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Contents
5.15.1.1 Detecting a System Lockup ................................................................. 174
5.15.1.2 Handling an Intruder ............................................................................ 174
5.15.1.3 Detecting Improper Firmware Hub Programming ................................ 175
5.15.2 Heartbeat and Event Reporting via SMBus ......................................................... 175
5.16 IDE Controller (D31:F1) .................................................................................................... 179
5.16.1 PIO Transfers ...................................................................................................... 179
5.16.1.1 PIO IDE Timing Modes ........................................................................ 179
5.16.1.2 IORDY Masking ................................................................................... 180
5.16.1.3 PIO 32-Bit IDE Data Port Accesses..................................................... 180
5.16.1.4 PIO IDE Data Port Prefetching and Posting ........................................ 180
5.16.2 Bus Master Function............................................................................................ 181
5.16.2.1 Physical Region Descriptor Format ..................................................... 181
5.16.2.2 Bus Master IDE Timings ...................................................................... 182
5.16.2.3 Interrupts.............................................................................................. 182
5.16.2.4 Bus Master IDE Operation ................................................................... 182
5.16.2.5 Error Conditions ................................................................................... 183
5.16.3 Ultra ATA/100/66/33 Protocol .............................................................................. 184
5.16.3.1 Operation ............................................................................................. 184
5.16.4 Ultra ATA/33/66/100 Timing ................................................................................ 185
5.16.5 ATA Swap Bay..................................................................................................... 185
5.16.6 SMI Trapping ....................................................................................................... 185
5.17 SATA Host Controller (D31:F2) ........................................................................................ 186
5.17.1 Theory of Operation............................................................................................. 186
5.17.1.1 Standard ATA Emulation ..................................................................... 186
5.17.1.2 48-Bit LBA Operation ........................................................................... 187
5.17.2 SATA Swap Bay Support..................................................................................... 187
5.17.3 Intel^® Matrix Storage Technology Configuration (ICH6R Only) ........................... 187
5.17.3.1 Intel^® Application Accelerator RAID Option ROM................................ 187
5.17.4 Power Management Operation............................................................................ 188
5.17.4.1 Power State Mappings......................................................................... 188
5.17.4.2 Power State Transitions....................................................................... 189
5.17.4.3 SMI Trapping (APM) ............................................................................ 190
5.17.5 SATA LED ........................................................................................................... 190
5.17.6 AHCI Operation ................................................................................................... 190
5.18 High Precision Event Timers ............................................................................................ 191
5.18.1 Timer Accuracy.................................................................................................... 191
5.18.2 Interrupt Mapping................................................................................................. 191
5.18.3 Periodic vs. Non-Periodic Modes......................................................................... 192
5.18.4 Enabling the Timers............................................................................................. 192
5.18.5 Interrupt Levels .................................................................................................... 193
5.18.6 Handling Interrupts .............................................................................................. 193
5.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors...................................... 193
5.19 USB UHCI Host Controllers (D29:F0, F1, F2, and F3) ..................................................... 194
5.19.1 Data Structures in Main Memory ......................................................................... 194
5.19.2 Data Transfers to/from Main Memory .................................................................. 194
5.19.3 Data Encoding and Bit Stuffing............................................................................ 194
5.19.4 Bus Protocol ........................................................................................................ 194
5.19.4.1 Bit Ordering.......................................................................................... 194
5.19.4.2 SYNC Field .......................................................................................... 194
5.19.4.3 Packet Field Formats ........................................................................... 195
5.19.4.4 Address Fields ..................................................................................... 195
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet