82801FB Datasheet, PDF (749/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Electrical Characteristics
Table 22-14. Ultra ATA Timing (Mode 3, Mode 4, Mode 5) (Sheet 1 of 2)
Sym
Parameter1
Mode 3
(ns)
Min Max
Mode 4
(ns)
Min Max
Mode 5
(ns)
Min Max
Measuring
Location
Figure
t80
Sustained Cycle Time
(T2cyctyp)
90
60
40
Sender
Connector
t81 Cycle Time (Tcyc)
End
39 – 25 – 16.8 – Recipient 22-10
Connector
t82 Two Cycle Time (T2cyc)
86
–
57
–
38
–
Sender
Connector
22-10
t83 Data Setup Time (Tds)
7
–
5
–
4.0
–
Recipient
Connector
22-10
Recipient IC data setup time
t83b (from data valid until STROBE
edge) (see Note 2) (Tdsic)
6.8 – 4.8 –
2.3 – ICH6 Balls
t84 Data Hold Time (Tdh)
5
–
5
–
4.6
–
Recipient
Connector
22-10
Recipient IC data hold time
t84b
(from STROBE edge until data
may become invalid) (see Note
4.8
–
4.8
–
2.8
–
ICH6 Balls
2) (Tdhic)
t85 Data Valid Setup Time (Tdvs)
20
–
6.7
–
4.8
–
Sender
22-9
Connector 22-10
Sender IC data valid setup time
t85b (from data valid until STROBE 22.6 – 9.5 – 6.0 – ICH6 Balls
edge) (see Note 2) (Tdvsic)
t86 Data Valid Hold Time (Tdvh)
6.2
–
6.2
–
4.8
–
Sender
22-9
Connector 22-10
Sender IC data valid hold time
t86b
(from STROBE edge until data
may become invalid) (see Note
9.0
–
9.0
–
6.0
–
ICH6 Balls
2) (Tdvhic)
t87 Limited Interlock Time (Tli)
0 100 0 100 0 75
Note 2 22-12
t88
Interlock Time w/ Minimum
(Tmli)
20
–
20
–
20
–
Host
Connector
22-12
t89 Envelope Time (Tenv)
20
55
20
55
20
50
Host
Connector
22-10
t90 Ready to Pause Time (Trp)
100 – 100 –
85
–
Recipient
Connector
22-11
t91
DMACK setup/hold Time (Tack) 20
–
20
–
20
–
Host
Connector
22-12
t92a
CRC Word Setup Time at Host
(Tcvs)
20
–
6.7
–
10
–
Host
Connector
CRC Word Hold Time at Sender
CRC word valid hold time at
t92b _{sender (from DMACK# negation} 6.2
–
6.2
– 10.0 –
Host
Connector
until CRC may become invalid)
(see Note 2) (Tcvh)
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
749