82801FB Datasheet, PDF (532/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

EHCI Controller Registers (D29:F7)
14.1.9
PMLT—Primary Master Latency Timer Register
(USB EHCI—D29:F7)
Address Offset: 0Dh
Default Value: 00h
Attribute: RO
Size:
8 bits
Bit
Description
Master Latency Timer Count (MLTC) — RO. Hardwired to 00h. Because the EHCI controller is
7:0 internally implemented with arbitration on an interface (and not PCI), it does not need a master
latency timer.
14.1.10
MEM_BASE—Memory Base Address Register
(USB EHCI—D29:F7)
Address Offset: 10–13h
Default Value: 00000000h
Attribute: R/W, RO
Size:
32 bits
Bit
Description
31:10
9:4
Base Address — R/W. Bits [31:10] correspond to memory address signals [31:10], respectively.
This gives 1-KB of locatable memory space aligned to 1-KB boundaries.
Reserved
3 Prefetchable — RO. Hardwired to 0 indicating that this range should not be prefetched.
2:1
Type — RO. Hardwired to 00b indicating that this range can be mapped anywhere within 32-bit
address space.
0
Resource Type Indicator (RTE) — RO. Hardwired to 0 indicating that the base address field in this
register maps to memory space.
14.1.11
SVID—USB EHCI Subsystem Vendor ID Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
Reset:
2C–2Dh
XXXXh
None
Attribute: R/W (special)
Size:
16 bits
Bit
Description
Subsystem Vendor ID (SVID) — R/W (special). This register, in combination with the USB 2.0
Subsystem ID register, enables the operating system to distinguish each subsystem from the others.
15:0
NOTE: Writes to this register are enabled when the WRT_RDONLY bit (D29:F7:80h, bit 0) is set
to 1.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet