82801FB Datasheet, PDF (579/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SMBus Controller Registers (D31:F3)
15.2.18 NOTIFY_DLOW—Notify Data Low Byte Register
(SMBus—D31:F3)
Register Offset: SMBASE + 16h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit
Description
DATA_LOW_BYTE — RO. This field contains the first (low) byte of data received during the Host
7:0 Notify protocol of the SMBus 2.0 specification. Software should only consider this field valid when
the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0) is set to 1.
15.2.19 NOTIFY_DHIGH—Notify Data High Byte Register
(SMBus—D31:F3)
Register Offset: SMBASE + 17h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit
Description
DATA_HIGH_BYTE — RO. This field contains the second (high) byte of data received during the
7:0 Host Notify protocol of the SMBus 2.0 specification. Software should only consider this field valid
when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0) is set to 1.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
579