82801FB Datasheet, PDF (105/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.2.4.4
SMI/SCI Generation
Interrupts for Hot-Plug events are not supported on legacy operating systems. To support Hot-Plug
on non-PCI Express aware operating systems, Hot-Plug events can be routed to generate SCI. To
generate SCI, MPC.HPCE (D28:F0/F1/F2/F3:Offset D8h:bit 30) must be set. When set, enabled
Hot-Plug events will cause SMSCS.HPCS (D28:F0/F1/F2/F3:Offset DCh:bit 30) to be set.
Additionally, BIOS workarounds for Hot-Plug can be supported by setting MPC.HPME (D28:F0/
F1/F2/F3:Offset D8h:bit 1). When this bit is set, Hot-Plug events can cause SMI status bits in
SMSCS to be set. Supported Hot-Plug events and their corresponding SMSCS bit are:
• Command Completed – SMSCS.HPCCM (D28:F0/F1/F2/F3:Offset DCh:bit 3)
• Presence Detect Changed – SMSCS.HPPDM (D28:F0/F1/F2/F3:Offset DCh:bit 1)
• Attention Button Pressed – SMSCS.HPABM (D28:F0/F1/F2/F3:Offset DCh:bit 2)
When any of these bits are set, SMI # will be generated. These bits are set regardless of whether
interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur concurrently with an
interrupt or SCI.
5.3
LAN Controller (B1:D8:F0)
The ICH6’s integrated LAN controller includes a 32-bit PCI controller that provides enhanced
scatter-gather bus mastering capabilities and enables the LAN controller to perform high-speed
data transfers over the PCI bus. Its bus master capabilities enable the component to process high
level commands and perform multiple operations; this lowers processor utilization by off-loading
communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB each, help
prevent data underruns and overruns while waiting for bus accesses. This enables the integrated
LAN controller to transmit data with minimum interframe spacing (IFS).
The ICH6 integrated LAN controller can operate in either full-duplex or half-duplex mode. In full-
duplex mode the LAN controller adheres with the IEEE 802.3x Flow Control Specification. Half
duplex performance is enhanced by a proprietary collision reduction mechanism.
The integrated LAN controller also includes an interface to a serial (4-pin) EEPROM. The
EEPROM provides power-on initialization for hardware and software configuration parameters.
From a software perspective, the integrated LAN controller appears to reside on the secondary side
of the ICH6’s virtual PCI-to-PCI bridge (see Section 5.1.6). This is typically Bus 1, but may be
assigned a different number, depending upon system configuration.
The following summarizes the ICH6 LAN controller features:
• Compliance with Advanced Configuration and Power Interface and PCI Power Management
standards
• Support for wake-up on interesting packets and link status change
• Support for remote power-up using Wake on LAN* (WOL) technology
• Deep power-down mode support
• Support of Wired for Management (WfM) Revision 2.0
• Backward compatible software with 82550, 82557, 82558 and 82559
• TCP/UDP checksum off load capabilities
• Support for Intel’s Adaptive Technology
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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