82801FB Datasheet, PDF (278/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Chipset Configuration Registers
Bit
Description
UHCI #2 Disable (U2D) — R/W. Default is 0.
9
0 = The 2nd UHCI (ports 2 and 3) is enabled.
1 = The 2nd UHCI (ports 2 and 3) is disabled.
UHCI #1 Disable (U1D) — R/W. Default is 0.
8
0 = The 1st UHCI (ports 0 and 1) is enabled.
1 = The 1st UHCI (ports 0 and 1) is disabled.
Hide Internal LAN (HIL) — R/W. Default is 0.
7
0 = The LAN controller is enabled.
1 = The LAN controller is disabled and will not decode configuration cycles off of PCI.
AC ‘97 Modem Disable (AMD) — R/W. Default is 0.
6
0 = The AC ‘97 modem function is enabled.
1 = The AC ‘97 modem function is disabled.
AC ‘97 Audio Disable (AAD) — R/W. Default is 0.
5
0 = The AC ‘97 audio function is enabled.
1 = The AC ‘97 audio function is disabled.
Intel High Definition Audio Disable (ZD) — R/W. Default is 0.
4
0 = The Intel High Definition Audio controller is enabled.
1 = The Intel High Definition Audio controller is disabled and its PCI configuration space is not
accessible.
SM Bus Disable (SD) — R/W. Default is 0.
3
0 = The SM Bus controller is enabled.
1 = The SM Bus controller is disabled. In ICH5 and previous, this also disabled the I/O space. In
ICH6, it only disables the configuration space.
Serial ATA Disable (SAD) — R/W. Default is 0.
2
0 = The SATA controller is enabled.
1 = The SATA controller is disabled.
Parallel ATA Disable (PAD) — R/W. Default is 0.
1
0 = The PATA controller is enabled.
1 = The PATA controller is disabled and its PCI configuration space is not accessible.
0
Reserved
7.1.57
CG—Clock Gating
Offset Address: 341C–341Fh
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32-bit
Bit
Description
31:1 Reserved
PCI Express root port Static Clock Gate Enable (PESCG) — R/W.
0 = Static Clock Gating is Disabled for the PCI Express* root port.
1 = Static Clock Gating is Enabled for the PCI Express root port when the corresponding port is
disabled in the Function Disable register (Chipset Configuration Registers:Offset 3418h)
0
FD.PE1D, FD.PE2D, FD.PE3D or FD.PE4D.
In addition to the PCI Express function disable register, the PCI Express root port physical layer
static clock gating is also qualified by the Root Port Configuration RPC.PC (Chipset Configuration
Registers:Offset 0224h:bits 1:0) as the physical layer may be required by an enabled port in a x4
configuration.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet