82801FB Datasheet, PDF (360/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
Bit
Description
FWH_Legacy_E_EN — R/W. This bit enables the decoding of the legacy 128-K range at E0000h –
EFFFFh.
6 _{0 = Disable.}
1 = Enable the following legacy ranges for the Firmware Hub
E0000h – EFFFFh
5:4 Reserved
FWH_70_EN — R/W. This bit enables decoding two 1-M Firmware Hub memory ranges.
0 = Disable.
3 _{1 = Enable the following ranges for the Firmware Hub}
FF70 0000h – FF7F FFFFh
FF30 0000h – FF3F FFFFh
FWH_60_EN — R/W. This bit enables decoding two 1-M Firmware Hub memory ranges.
0 = Disable.
2 _{1 = Enable the following ranges for the Firmware Hub}
FF60 0000h – FF6F FFFFh
FF20 0000h – FF2F FFFFh
FWH_50_EN — R/W. This bit enables decoding two 1-M Firmware Hub memory ranges.
0 = Disable.
1 _{1 = Enable the following ranges for the Firmware Hub}
FF50 0000h – FF5F FFFFh
FF10 0000h – FF1F FFFFh
FWH_40_EN — R/W. This bit enables decoding two 1-M Firmware Hub memory ranges.
0 = Disable.
0 _{1 = Enable the following ranges for the Firmware Hub}
FF40 0000h – FF4F FFFFh
FF00 0000h – FF0F FFFFh
10.1.26
BIOS_CNTL—BIOS Control Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
DCh
00h
No
Attribute:
Size:
Power Well:
R/WLO, R/W
8 bit
Core
Bit
Description
7:2 Reserved
BIOS Lock Enable (BLE) — R/WLO.
1 ^{0 = Setting the BIOSWE will not cause SMIs.}
1 = Enables setting the BIOSWE bit to cause SMIs. Once set, this bit can only be cleared by a
PLTRST#
BIOS Write Enable (BIOSWE) — R/W.
0 = Only read cycles result in Firmware Hub I/F cycles.
0 _{1 = Access to the BIOS space is enabled for both read and write cycles. When this bit is written}
from a 0 to a 1 and BIOS Lock Enable (BLE) is also set, an SMI# is generated. This ensures
that only SMI code can update BIOS.
360
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet