82801FB Datasheet, PDF (744/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Electrical Characteristics
Table 22-9. Clock Timings (Sheet 2 of 2)
Sym
Parameter
Min Max Unit Figure
AC ’97 Clock (ACZ_BIT_CLK - AC ‘97 mode)
fac97 Operating Frequency
t26 Input Jitter (refer to Clock Chip Specification)
12.288
–
2
MHz
ns
t27
t28
t29
t30
fHDA
High time
36
45
Low time
36
45
Rise time
2.0
6.0
Fall time
2.0
6.0
ACZ_BIT_CLK (Intel High Definition Audio Mode)
Operating Frequency
24.0
Frequency Tolerance
–
100
ns
ns
ns
ns
MHz
ppm
22-1
22-1
22-1
22-1
t26a Input Jitter (refer to Clock Chip Specification)
–
300
ppm
t27a High Time (Measured at 0.75Vcc)
t28a Low Time (Measured at 0.35Vcc)
18.75 22.91
ns
18.75 22.91
ns
22-1
22-1
SATA Clock (SATA_CLKP, SATA_CLKN) / DMI Clock (DMI_CLKP, DMI_CLKN)
t36 Period
t37 Rise time
t38 Fall time
9.997 10.003 ns
175
700
ps
175
700
ps
Suspend Clock (SUSCLK)
fsusclk Operating Frequency
t39 High Time
32
kHz
10
–
us
t40 Low Time
10
–
us
Notes
4
5
5
6
6
6
NOTES:
1. CLK14 edge rates in a system as measured from 0.8 V to 2.0 V.
2. The CLK48 expects a 40/60% duty cycle.
3. The maximum high time (t18 Max) provide a simple guaranteed method for devices to detect bus idle
conditions.
4. The ICh6 can tolerate a maximum of 2 ns of jitter from the input BITCLK. Note that clock jitter may impact
system timing. If routing guidelines for AC ‘97 were not followed as published in the Platform Design Guides,
system designers should ensure the input clock jitter does not negatively impact the system timing.
5. BITCLK Rise and Fall times are measured from 10%VDD and 90%VDD.
6. SUSCLK duty cycle can range from 30% minimum to 70% maximum.
744
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet