SH7713 Datasheet, PDF (99/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Instruction
Instruction Code Operation
Privileged
Mode
Cycles T Bit
DT
Rn
0100nnnn00010000 Rn – 1 → Rn, if Rn = 0, 1 → T, 
else 0 → T
1
Comparison
result
EXTS.B
Rm,Rn
0110nnnnmmmm1110 A byte in Rm is sign-extended 
→ Rn
1

EXTS.W Rm,Rn
0110nnnnmmmm1111 A word in Rm is sign-extended 
→ Rn
1

EXTU.B
Rm,Rn
0110nnnnmmmm1100 A byte in Rm is zero-extended 
→ Rn
1

EXTU.W Rm,Rn
0110nnnnmmmm1101 A word in Rm is zero-extended 
→ Rn
1

MAC.L
@Rm+, 0000nnnnmmmm1111 Signed operation of (Rn) ×

@Rn+
(Rm) + MAC → MAC,Rn + 4
→ Rn, Rm + 4 → Rm,
32 × 32 + 64 → 64 bits
2 (to 5)* 
MAC.W
@Rm+, 0100nnnnmmmm1111 Signed operation of (Rn) ×

@Rn+
(Rm) + MAC → MAC,Rn + 2
→ Rn, Rm + 2 → Rm,
16 × 16 + 64 → 64 bits
2 (to 5)* 
MUL.L
Rm,Rn
0000nnnnmmmm0111 Rn × Rm → MACL,
32 × 32 → 32 bits

2 (to 5)* 
MULS.W Rm,Rn
0010nnnnmmmm1111 Signed operation of Rn × Rm 
→ MACL,
16 × 16 → 32 bits
1( to 3)* 
MULU.W Rm,Rn 0010nnnnmmmm1110 Unsigned operation of

1(to 3)* 
Rn × Rm → MACL,
16 × 16 → 32 bits
NEG
Rm,Rn 0110nnnnmmmm1011 0–Rm→Rn

1

NEGC
Rm,Rn 0110nnnnmmmm1010 0–Rm–T→Rn, Borrow→T

1
Borrow
SUB
Rm,Rn 0011nnnnmmmm1000 Rn–Rm→Rn

1

SUBC
Rm,Rn 0011nnnnmmmm1010 Rn–Rm–T→Rn, Borrow →T 
1
Borrow
SUBV
Rm,Rn 0011nnnnmmmm1011 Rn–Rm→Rn, Underflow→T 
1
Underflow
Note: * The number of execution cycles indicated within the parentheses ( ) are required when
the operation result is read from the MACH/MACL register immediately after the
instruction.
Rev.1.50 Aug. 30, 2006 Page 59 of 860
REJ09B0288-0150