SH7713 Datasheet, PDF(179/904 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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SH7713 Datasheet, PDF (179/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Section 3 DSP Operating Unit

3.5.13 Operand Conflict

When an identical destination operand is specified with multiple parallel instructions, data conflict

occurs. Table 3.34 shows the correspondence between each operand and registers.

Table 3.34 Correspondence between Operands and Registers

X-Memory

Load

Y-Memory

Load

6-operand ALU

3-operand

Multiply

Ax Ix Dx Ay Iy Dy Sx Sy Du Se Sf Dg

DSP

A0

Registers A1

*1

*2

*2

*1

*2

*1

*1

*2

M0

*1

*1

M1

*1

*1

X0

*2

*1

*2

*1

*1

X1

*2

*1

*1

Y0

*2

*1

*2

*1

*1

Y1

*2

*1

*1

Notes: 1. Registers available for operands

2. Registers available for operands (when there is operand conflict)

3-operand ALU

Sx Sy Dz

*1

*1

*1

*1

*1

*1

*1

*1

*1

*2

*1

*2

*1

*2

*1

*2

There are three cases of operand conflict problems.

â¢ When ALU operation and multiply instructions specify the same destination operand (Du and

Dg)

â¢ When X-memory load and ALU operation specify the same destination operand (Dx and Du,

or Dz)

â¢ When Y-memory load and ALU operation specify the same destination operand (Dy and Du,

or Dz)

In these cases above, the result is not guaranteed.

Rev.1.50 Aug. 30, 2006 Page 139 of 860

REJ09B0288-0150

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