SH7713 Datasheet, PDF (321/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 User Break Controller
9.2.14 Break ASID Register B (BASRB)
BASRB is an 8-bit readable/writable register that specifies ASID which becomes the break
condition for channel B. BASRB is in CCN.
Initial
Bit Bit Name Value R/W
7 to 0 BASB7 to 
R/W
BASB0
Description
Break ASID B
Store ASID (bits 7 to 0) which is the break condition for
channel B.
9.3 Operation
9.3.1 Flow of the User Break Operation
The flow from setting of break conditions to user break exception processing is described below:
1. The break addresses and corresponding ASID are set in the break address registers (BARA or
BARB) and break ASID registers (BASRA or BASRB in CCN). The masked addresses are set
in the break address mask registers (BAMRA or BAMRB). The break data is set in the break
data register (BDRB). The masked data is set in the break data mask register (BDMRB). The
bus break conditions are set in the break bus cycle registers (BBRA or BBRB). Three groups
of BBRA or BBRB (L bus cycle/I bus cycle select, instruction fetch/data access select, and
read/write select) are each set. No user break will be generated if even one of these groups is
set with 00. The respective conditions are set in the bits of the break control register (BRCR).
Make sure to set all registers related to breaks before setting BBRA or BBRB.
2. When the break conditions are satisfied, the UBC sends a user break request to the CPU and
sets the L bus condition match flag (SCMFCA or SCMFCB) and the I bus condition match
flag (SCMFDA or SCMFDB) for the appropriate channel. When the X/Y memory bus is
specified for channel B, SCMFCB is used for the condition match flag.
3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can
be used to check if the set conditions match or not. The matching of the conditions sets flags,
but they are not reset. 0 must first be written to them before they can be used again.
4. There is a chance that the break set in channel A and the break set in channel B occur around
the same time. In this case, there will be only one break request to the CPU, but these two
break channel match flags could be both set.
5. When selecting the I bus as the break condition, note the following:
Rev.1.50 Aug. 30, 2006 Page 281 of 860
REJ09B0288-0150