SH7713 Datasheet, PDF (295/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
8.4.8 Interrupt Request Register 4 (IRR4)
IRR4 is an 8-bit register that indicates whether interrupt requests from the TMU2, TMU1, TMU0,
WDT, and REF are generated. This register is initialized to H'00 by a power-on reset or manual
reset, but is not initialized in standby mode.
Bit
Bit Name Initial Value R/W Description
7

0
R
Reserved
This bit always read as 0. The write value
should always be 0.
6
TUNI2R
0
R
TUNI2 Interrupt Request
Indicates whether the TUNI2 (TMU2) interrupt
request is generated.
0: TUNI2 interrupt request is not generated
1: TUNI2 interrupt request is generated
5
TUNI1R
0
R
TUNI1Interrupt Request
Indicates whether the TUNI1 (TMU1) interrupt
request is generated.
0: TUNI1 interrupt request is not generated
1: TUNI1 interrupt request is generated
4
TUNI0R
0
R
TUNI0 Interrupt Request
Indicates whether the TUNI0 (TMU0) interrupt
request is generated.
0: TUNI0 interrupt request is not generated
1: TUNI0 interrupt request is generated
3
ITIR
0
R
ITI Interrupt Request
Indicates whether the ITI (WDT) interrupt
request is generated.
0: ITI interrupt request is not generated
1: ITI interrupt request is generated
2

0
R
Reserved
1

0
R
These bits are always read as 0. The write value
should always be 0.
Rev.1.50 Aug. 30, 2006 Page 255 of 860
REJ09B0288-0150