SH7713 Datasheet, PDF(458/904 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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SH7713 Datasheet, PDF (458/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Section 12 Bus State Controller (BSC)

Single Read: A read access ends in one cycle when data exists in non-cachable region and the

data bus width is larger than or equal to access size. As the burst length is set to 1 in synchronous

DRAM burst read/single write mode, only the required data is output. Consequently, no

unnecessary bus cycles are generated even when a cache-through area is accessed.

Figure 12.16 shows the single read basic timing.

CKIO

A25 to A0

A12/A11*1

CSn

RAS

CAS

RD/WR

DQMxx

D31 to D0

BS

DACKn*2

Tr

Tc1

Td1

Tde

Tap

Notes: 1. Address pin to be connected to the A10 pin of SDRAM.

2. The waveform for DACKn is when active low is specified.

Figure 12.16 Basic Timing for Single Read (Auto Precharge)

Rev.1.50 Aug. 30, 2006 Page 418 of 860

REJ09B0288-0150

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