SH7713 Datasheet, PDF (586/904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value
7
ER
0
R/W
R/(W)*
Description
Receive Error
Indicates that a framing error or parity error
occurred during reception.*¹
0: No framing error or parity error occurred during
reception
[Clearing conditions]
• Power-on reset or manual reset
• When 0 is written to ER after reading ER = 1
1: A framing error or parity error occurred during
reception
[Setting conditions]
• When the SCIF checks whether the stop bit at
the end of the receive data is 1 when reception
ends, and the stop bit is 0*²
• When, in reception, the number of 1-bits in the
receive data plus the parity bit does not match
the parity setting (even or odd) specified by the
O/E bit in SCSMR
Notes: 1. The ER flag is not affected and retains
its previous state when the RE bit in
SCSCR is cleared to 0. When a receive
error occurs, the receive data is still
transferred to SCFRDR, and reception
continues.
The FER and PER bits in SCFSR can
be used to determine whether there is a
receive error in the data read from
SCFRDR.
2. When the stop length is 2 bits, only the
first stop bit is checked for a value of 1;
the second stop bit is not checked.
Rev.1.50 Aug. 30, 2006 Page 546 of 860
REJ09B0288-0150